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AB28F200BR-T80

更新时间： 2024-02-08 02:01:36

品牌	Logo	应用领域
英特尔 - INTEL		闪存存储内存集成电路光电二极管
页数	文件大小	规格书
36页	438K
描述
2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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AB28F200BR-T80 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	SOIC	包装说明：	0.525 X 1.110 INCH, PLASTIC, SOP-44
针数：	44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.69	Is Samacsys：	N
最长访问时间：	80 ns	其他特性：	USER CONFIGURABLE 5V OR 12V VPP; DEEP POWER DOWN; TOP BOOT BLOCK; HARDWARE WRITE PROTECT
备用内存宽度：	8	启动块：	TOP
命令用户界面：	YES	数据轮询：	NO
JESD-30 代码：	R-PDSO-G44	JESD-609代码：	e0
长度：	28.2 mm	内存密度：	2097152 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	部门数/规模：	1,2,1,1
端子数量：	44	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	256KX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP44,.63	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	PARALLEL
电源：	5 V	编程电压：	5 V
认证状态：	Not Qualified	座面最大高度：	2.95 mm
部门规模：	16K,8K,96K,128K	最大待机电流：	0.00001 A
子类别：	Flash Memories	最大压摆率：	0.07 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	MOS	温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
切换位：	NO	类型：	NOR TYPE
宽度：	13.3 mm	Base Number Matches：	1

AB28F200BR-T80 数据手册

A28F200BR

Savings (APS) feature which minimizes system

battery current drain, allowing for very low power

designs. To provide even greater power savings,

the boot block family includes a deep power-down

mode which minimizes power consumption by

turning most of the flash memory’s circuitry off.

This mode is controlled by the RP# pin and its

usage is discussed in Section 3.5, along with other

power consumption issues.

When the product is in the end-user’s hands, and

updates or feature enhancements become

necessary or mandatory, flash memory eliminates

the need to replace an assembly. The update can

be performed as part of routine maintenance

operation

relatively

unsophisticated

technicians.

The reliability of such a field upgrade is enhanced

by a hardware-protected 16-Kbyte boot block. If

the protection methods are implemented in the

circuit design, the boot block will be

unchangeable. Locating the boot-strap code in this

area assures a fail-safe recovery from an update

operation that failed to complete correctly.

Additionally, the RP# pin provides protection

against unwanted command writes due to invalid

system bus conditions that may occur during

system reset and power-up/down sequences.

Also, when the flash memory powers-up, it

automatically defaults to the read array mode, but

during

warm system reset, where power

The two 8-Kbyte parameter blocks allow

modification of control algorithms to reflect

changes in the process or device being controlled.

A variety of software algorithms allow these two

blocks to behave like a standard EEPROM.

continues uniterrupted to the system components,

the flash memory could remain in a non-read

mode, such as erase. Consequently, the system

Reset pin should be tied to RP# to reset the

memory to normal read mode upon activation of

the Reset pin.

Intel’s boot block architecture provides a flexible

voltage solution for the different design needs of

various applications. The asymmetrically-blocked

memory map allows the integration of several

memory components into a single flash device.

The boot block provides a secure boot PROM; the

parameter blocks can emulate EEPROM

functionality for parameter store with proper

software techniques; and the main blocks provide

code and data storage with access times fast

enough to execute code in place, decreasing RAM

requirements.

The byte-wide or word-wide input/output is

controlled by the BYTE# pin. See Table 1 for a

detailed description of BYTE# operations,

especially the usage of the DQ₁₅/A_-1pin.

The 28F200 products are available in

ROM/EPROM-compatible pinout and housed in

the 44-lead PSOP (Plastic Small Outline)

package.

Refer to the DC Characteristics Table, Section 5.2

for complete current and voltage specifications.

Refer to the AC Characteristics Table, Section

5.3, for read, program and erase performance

specifications.

1.4

Pinouts

Intel’s SmartVoltage boot block architecture

provides upgrade paths in every package pinout to

the 8-Mbit density. The 28F200 44-lead PSOP

pinout follows the industry standard ROM/EPROM

pinout as shown in Figure 2.

1.3

Applications

The 2-Mbit boot block flash memory family

combines high-density, low-power, high-

Pinouts for the corresponding 4-Mbit and 8-Mbit

components are also provided for convenient

reference. 2-Mbit pinouts are given on the chip

illustration in the center, with 2-Mbit and 8-Mbit

pinouts going outward from the center.

performance, cost-effective flash memories with

blocking and hardware protection capabilities.

Their flexibility and versatility reduce costs

throughout the product life cycle. Flash memory is

ideal for Just-In-Time production flow, reducing

system inventory and costs, and eliminating

component handling during the production phase.

ADVANCE INFORMATION

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与AB28F200BR-T80相关器件

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AB28F200BX-B90	INTEL	2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY	获取价格
AB28F200BX-T90	INTEL	2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY	获取价格
AB28F400B5B80	INTEL	5 VOLT BOOT BLOCK FLASH MEMORY	获取价格
AB28F400B5T80	INTEL	5 VOLT BOOT BLOCK FLASH MEMORY	获取价格
AB28F400BR-B80	NUMONYX	Flash, 512KX8, 80ns, PDSO44, 0.525 X 1.110 INCH, PLASTIC, SOP-44	获取价格
AB28F400BR-B80	INTEL	Flash, 512KX8, 80ns, PDSO44, 0.525 X 1.110 INCH, PLASTIC, SOP-44	获取价格

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