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A80960JD

更新时间: 2024-11-08 22:26:51
品牌 Logo 应用领域
英特尔 - INTEL 微处理器
页数 文件大小 规格书
59页 736K
描述
3.3 V EMBEDDED 32-BIT MICROPROCESSOR

A80960JD 数据手册

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PRODUCT PREVIEW  
80960JD  
3.3 V EMBEDDED 32-BIT MICROPROCESSOR  
• 3.3 V, 5 V Tolerant, Version of the 80960JD Processor  
Pin/Code Compatible with all 80960Jx  
3.3 V Supply Voltage  
— 5 V Tolerant Inputs  
Processors  
— TTL Compatible Outputs  
High-Performance Embedded Architecture  
— One Instruction/Clock Execution  
— Core Clock Rate is 2x the Bus Clock  
— Load/Store Programming Model  
— Sixteen 32-Bit Global Registers  
— Sixteen 32-Bit Local Registers (8 sets)  
— Nine Addressing Modes  
High Bandwidth Burst Bus  
— 32-Bit Multiplexed Address/Data  
— Programmable Memory Configuration  
— Selectable 8-, 16-, 32-Bit Bus Widths  
— Supports Unaligned Accesses  
— Big or Little Endian Byte Ordering  
— User/Supervisor Protection Model  
High-Speed Interrupt Controller  
— 31 Programmable Priorities  
Two-Way Set Associative Instruction Cache  
— 80960JD - 4 Kbyte  
— Eight Maskable Pins plus NMI  
— Up to 240 Vectors in Expanded Mode  
— Programmable Cache Locking  
Mechanism  
Two On-Chip Timers  
Direct Mapped Data Cache  
— 80960JD - 2 Kbyte  
— Independent 32-Bit Counting  
— Clock Prescaling by 1, 2, 4 or 8  
— lnternal Interrupt Sources  
— Write Through Operation  
Halt Mode for Low Power  
On-Chip Stack Frame Cache  
— Seven Register Sets Can Be Saved  
— Automatic Allocation on Call/Return  
— 0-7 Frames Reserved for High-Priority  
Interrupts  
IEEE 1149.1 (JTAG) Boundary Scan  
Compatibility  
Packages  
— 132-Lead Pin Grid Array (PGA)  
— 132-Lead Plastic Quad Flat Pack (PQFP)  
On-Chip Data RAM  
— 1 Kbyte Critical Variable Storage  
— Single-Cycle Access  
132  
PIN 1  
99  
A80960JD  
®
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i960  
M
©
19xx  
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NG80960JD  
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M
©
19xx  
i
33  
66  
Figure 1. 80960JD Microprocessor  
November 1996  
© INTEL CORPORATION, 1996  
Order Number: 272971-001  

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