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A80960JF-25 PDF预览

A80960JF-25

更新时间: 2024-11-06 22:07:39
品牌 Logo 应用领域
英特尔 - INTEL 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
78页 825K
描述
EMBEDDED 32-BIT MICROPROCESSOR

A80960JF-25 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:PGA包装说明:PGA, PGA132,14X14
针数:132Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
其他特性:OPERATING CASE TEMPERATURE 0 TO 100 C地址总线宽度:32
位大小:32边界扫描:YES
最大时钟频率:25 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:YES
JESD-30 代码:S-CPGA-P132JESD-609代码:e0
长度:37.08 mm低功率模式:YES
端子数量:132封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA132,14X14
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
速度:25 MHz子类别:Microprocessors
最大压摆率:260 mA最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:NO技术:CMOS
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:37.08 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

A80960JF-25 数据手册

 浏览型号A80960JF-25的Datasheet PDF文件第2页浏览型号A80960JF-25的Datasheet PDF文件第3页浏览型号A80960JF-25的Datasheet PDF文件第4页浏览型号A80960JF-25的Datasheet PDF文件第5页浏览型号A80960JF-25的Datasheet PDF文件第6页浏览型号A80960JF-25的Datasheet PDF文件第7页 
80960JA/JF/JD/JT 3.3 V EMBEDDED  
32-BIT MICROPROCESSOR  
Advance Information Datasheet  
Product Features  
Pin/Code Compatible with all 80960Jx  
On-Chip Data RAM  
Processors  
—1 Kbyte Critical Variable Storage  
—Single-Cycle Access  
High-Performance Embedded Architecture  
—One Instruction/Clock Execution  
3.3 V Supply Voltage  
—Core Clock Rate is:  
—5 V Tolerant Inputs  
80960JA/JF 1x the Bus Clock  
80960JD 2x the Bus Clock  
80960JT 3x the Bus Clock  
TTL Compatible Outputs  
High Bandwidth Burst Bus  
—32-Bit Multiplexed Address/Data  
—Programmable Memory Configuration  
—Selectable 8-, 16-, 32-Bit Bus Widths  
—Supports Unaligned Accesses  
—Big or Little Endian Byte Ordering  
High-Speed Interrupt Controller  
31 Programmable Priorities  
Eight Maskable Pins plus NMI  
Up to 240 Vectors in Expanded Mode  
Two On-Chip Timers  
Load/Store Programming Model  
—Sixteen 32-Bit Global Registers  
—Sixteen 32-Bit Local Registers (8 sets)  
—Nine Addressing Modes  
—User/Supervisor Protection Model  
Two-Way Set Associative Instruction  
Cache  
—80960JA - 2 Kbyte  
80960JF/JD - 4 Kbyte  
—80960JT - 16 Kbyte  
—Programmable Cache-Locking  
Mechanism  
Independent 32-Bit Counting  
—Clock Prescaling by 1, 2, 4 or 8  
lnternal Interrupt Sources  
Direct Mapped Data Cache  
—80960JA - 1 Kbyte  
Halt Mode for Low Power  
80960JF/JD - 2 Kbyte  
IEEE 1149.1 (JTAG) Boundary Scan  
80960JT - 4 Kbyte  
Compatibility  
Packages  
Write Through Operation  
On-Chip Stack Frame Cache  
—Seven Register Sets Can Be Saved  
—Automatic Allocation on Call/Return  
132-Lead Pin Grid Array (PGA)  
132-Lead Plastic Quad Flat Pack  
(PQFP)  
—196-Ball Mini Plastic Ball Grid Array  
(MPBGA)  
—0-7 Frames Reserved for High-Priority  
Interrupts  
Notice: This document contains information on products in the sampling and initial production  
phases of development. The specifications are subject to change without notice. Verify with your  
local Intel sales office that you have the latest datasheet before finalizing a design.  
Order Number: 273159-001  
March, 1998  

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