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A54SX16-2VQ100X79 PDF预览

A54SX16-2VQ100X79

更新时间: 2024-10-30 18:35:43
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟可编程逻辑
页数 文件大小 规格书
64页 487K
描述
Field Programmable Gate Array, 1452 CLBs, 16000 Gates, 320MHz, CMOS, PQFP100, 1 MM HEIGHT, MO-136, VQFP-100

A54SX16-2VQ100X79 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:TFQFP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.74
Is Samacsys:N其他特性:CAN ALSO BE OPERATED AT 5V; 24000 SYSTEM GATES ALSO AVAILABLE
最大时钟频率:320 MHzCLB-Max的组合延迟:0.7 ns
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm湿度敏感等级:3
可配置逻辑块数量:1452等效关口数量:16000
端子数量:100最高工作温度:70 °C
最低工作温度:组织:1452 CLBS, 16000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

A54SX16-2VQ100X79 数据手册

 浏览型号A54SX16-2VQ100X79的Datasheet PDF文件第2页浏览型号A54SX16-2VQ100X79的Datasheet PDF文件第3页浏览型号A54SX16-2VQ100X79的Datasheet PDF文件第4页浏览型号A54SX16-2VQ100X79的Datasheet PDF文件第5页浏览型号A54SX16-2VQ100X79的Datasheet PDF文件第6页浏览型号A54SX16-2VQ100X79的Datasheet PDF文件第7页 
v3.2  
SX Family FPGAs  
u
e
Leading Edge Performance  
Features  
320 MHz Internal Performance  
3.7 ns Clock-to-Out (Pin-to-Pin)  
0.1 ns Input Setup  
66 MHz PCI  
CPLD and FPGA Integration  
Single-Chip Solution  
100% Resource Utilization with 100% Pin Locking  
3.3 V and 5.0 V Operation with 5.0 V Input Tolerance  
Very Low Power Consumption  
Deterministic, User-Controllable Timing  
Unique In-System Diagnostic and Debug Capability  
with Silicon Explorer II  
0.25 ns Clock Skew  
Specifications  
12,000 to 48,000 System Gates  
Up to 249 User-Programmable I/O Pins  
Up to 1,080 Flip-Flops  
Boundary Scan Testing in Compliance with IEEE  
Standard 1149.1 (JTAG)  
Secure Programming Technology Prevents Reverse  
Engineering and Design Theft  
0.35 µ CMOS  
SX Product Profile  
Device  
A54SX08  
A54SX16  
A54SX16P  
A54SX32  
Capacity  
Typical Gates  
System Gates  
8,000  
12,000  
16,000  
24,000  
16,000  
24,000  
32,000  
48,000  
Logic Modules  
768  
512  
1,452  
924  
1,452  
924  
2,880  
1,800  
Combinatorial Cells  
Register Cells (Dedicated Flip-Flops)  
Maximum User I/Os  
Clocks  
256  
528  
528  
175  
1,080  
130  
175  
249  
3
Yes  
3
Yes  
3
3
Yes  
JTAG  
Yes  
PCI  
Yes  
Clock-to-Out  
3.7 ns  
0.8 ns  
Std, –1, –2, –3  
C, I, M  
3.9 ns  
0.5 ns  
Std, –1, –2, –3  
C, I, M  
4.4 ns  
0.5 ns  
Std, –1, –2, –3  
C, I, M  
4.6 ns  
0.1 ns  
Std, –1, –2, –3  
C, I, M  
Input Setup (external)  
Speed Grades  
Temperature Grades  
Packages (by pin count)  
PLCC  
PQFP  
VQFP  
TQFP  
PBGA  
FBGA  
84  
208  
100  
144, 176  
144  
208  
100  
176  
208  
100  
144, 176  
208  
144, 176  
313, 329  
June 2006  
i
© 2006 Actel Corporation  
See the Actel website for the latest version of the datasheet.  

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