Datasheet > A54SX16-2VQG100

A54SX16-2VQG100

更新时间： 2024-11-07 03:23:55

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
64页	487K
描述
Field Programmable Gate Array, 1452 CLBs, 16000 Gates, 320MHz, CMOS, PQFP100, 1 MM HEIGHT, ROHS COMPLIANT, MO-136, VQFP-100

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数据手册

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A54SX16-2VQG100 数据手册

v3.2

™

SX Family FPGAs

Leading Edge Performance

Features

•

320 MHz Internal Performance

3.7 ns Clock-to-Out (Pin-to-Pin)

0.1 ns Input Setup

•

66 MHz PCI

CPLD and FPGA Integration

Single-Chip Solution

100% Resource Utilization with 100% Pin Locking

3.3 V and 5.0 V Operation with 5.0 V Input Tolerance

Very Low Power Consumption

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Debug Capability

with Silicon Explorer II

0.25 ns Clock Skew

Specifications

•

12,000 to 48,000 System Gates

Up to 249 User-Programmable I/O Pins

Up to 1,080 Flip-Flops

•

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

Secure Programming Technology Prevents Reverse

Engineering and Design Theft

0.35 µ CMOS

SX Product Profile

Device

A54SX08

A54SX16

A54SX16P

A54SX32

Capacity

Typical Gates

System Gates

8,000

12,000

16,000

24,000

16,000

24,000

32,000

48,000

Logic Modules

768

512

1,452

924

1,452

924

2,880

1,800

Combinatorial Cells

Maximum User I/Os

Clocks

256

528

175

1,080

130

175

249

Yes

JTAG

Yes

PCI

–

Yes

–

Clock-to-Out

3.7 ns

0.8 ns

Std, –1, –2, –3

C, I, M

3.9 ns

0.5 ns

Std, –1, –2, –3

C, I, M

4.4 ns

0.5 ns

Std, –1, –2, –3

C, I, M

4.6 ns

0.1 ns

Std, –1, –2, –3

C, I, M

Input Setup (external)

Speed Grades

Temperature Grades

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

PBGA

FBGA

208

100

144, 176

–

144

–

208

100

176

–

208

100

144, 176

–

208

–

144, 176

313, 329

–

June 2006

See the Actel website for the latest version of the datasheet.

12 3 4 5 6 7...64

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