Datasheet > A42L8316S-30

A42L8316S-30

更新时间： 2022-11-25 16:57:13

品牌	Logo	应用领域
联笙电子 - AMICC		/
页数	文件大小	规格书
25页	274K
描述
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

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A42L8316S-30 数据手册

A42L8316 Series

AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)

Test Conditions:

Input timing reference level: VIH/VIL=2.0V/0.8V

Output reference level: VOH/VOL=2.0V/0.8V

Output Load: 2TTL gate + CL (50pF)

Assumed tT=2ns

-30

-35

-40

Std

Symbol

Parameter

Unit

Notes

Min. Max. Min.

Max.

Min. Max.

tOEZ

Output Buffer Turn-off Delay from

tRASS

100

RAS pulse width

(

-B- self refresh)

tRPS

tCHS

RAS precharge time

-B- self refresh)

(

-50

CAS hold time ( -B- self refresh)

Notes:

1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200ms is required after power-up followed by any 8 RAS cycles before proper device operation is

achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8

RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.

4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and

50pF, VIL (min.) ³ GND and VIH (max.) £ VCC.

5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH and VIL.

6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference

point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.

7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.

8. Assumes three state test load (5pF and a 500W Thevenin equivalent).

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output

voltage levels.

11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If tWCS ³ tWCS (min.) and tWCH ³ tWCH (min.), the cycle is an early write cycle

and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ³ tRWD (min.) , tCWD ³

tCWD (min.) and tAWD ³ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from

the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is

indeterminate.

12. These parameters are referenced to

read-modify-write cycles.

and

leading edge in early write cycles and to WE leading edge in

LCAS

UCAS

13. Access time is determined by the longer of tAA or tCAC or tCPA.

14. tASC ³ tCP to achieve tPC (min.) and tCPA (max.) values.

PRELIMINARY

(August, 2002, Version 0.1)

AMIC Technology, Inc.

1...7 8 91011 12 13...25

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与A42L8316S-30相关器件

型号	品牌	获取价格	描述	数据表
A42L8316S-35	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316S-35F	AMICC	获取价格	EDO DRAM, 256KX16, 35ns, CMOS, PDSO40, SOJ-40
A42L8316S-40	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316S-40F	AMICC	获取价格	EDO DRAM, 256KX16, 40ns, CMOS, PDSO40, SOJ-40
A42L8316SERIES	ETC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316V	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316V-30	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316V-30U	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316V-35	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42L8316V-35F	AMICC	获取价格	EDO DRAM, 256KX16, 35ns, CMOS, PDSO40, TSOP2-44/40

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