Datasheet > 9ZXL1252EKILF

9ZXL1252EKILF

更新时间： 2022-02-26 11:08:53

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
21页	254K
描述
12-Output DB1200ZL Derivative for PCIe Gen1â4 and UPI

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9ZXL1252EKILF 数据手册

12-Output DB1200ZL Derivative

for PCIe Gen1–4 and UPI with

Write Lock

9ZXL1232E / 9ZXL1252E

Datasheet

Description

Features

▪ SMBus write lock feature; increases system security

▪ LP-HCSL outputs; eliminate 24 resistors, save 41mm²of area

The 9ZXL1232E / 9ZXL1252E are second-generation,

enhanced-performance DB1200ZL differential buffers. The parts

are pin-compatible upgrades to the 9ZXL1232A and 9ZLX1252A,

while offering a much improved phase jitter performance and an

SMBus Write Lock feature for increased system security. A fixed

external feedback maintains low drift for critical QPI/UPI

applications. The 9ZXL1232E and 9ZXL1252E have an SMBus

Write Lockout pin for increased device and system security.

(1232E)

▪ LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save

82mm²of area (1252E)

▪ 12 OE# pins; hardware control of each output

▪ 9 selectable SMBus addresses; multiple devices can share the

same SMBus segment

▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL

PCIe Clocking Architectures

Supported

topologies

▪ Hardware/SMBus control of PLL bandwidth and bypass;

▪ Common Clocked (CC)

change mode without power cycle

▪ Independent Reference (IR) with and without spread spectrum

▪ Spread spectrum compatible; tracks spreading input clock for

EMI reduction

▪ 100MHz & 133.33MHz PLL mode; UPI and legacy QPI support

▪ 9 x 9 mm 64-QFN package; small board footprint

Typical Applications

▪ Servers

▪ Storage

▪ Networking

▪ SSDs

Key Specifications

▪ Cycle-to-cycle jitter < 50ps

▪ Output-to-output skew < 50ps

▪ Input-to-output delay: Fixed at 0ps

▪ Input-to-output delay variation < 50ps

▪ Phase jitter: PCIe Gen4 < 0.5ps rms

▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms

▪ Phase jitter: IF-UPI < 1.0ps rms

Output Features

▪ 12 Low-Power (LP) HCSL output pairs (1232E)

▪ 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1252E)

Block Diagram

VDDR

VDDA

VDD x3

VDDIO x4

FBOUT_NC#

FBOUT_NC

PLL

DIF_IN#

DIF_IN

DIF11#

DIF11

^100M_133M#

vSADR[1:0]_tri

SMBCLK

outputs

SMBus

Engine Configuration

Factory

SMBDAT

vSMB_WRTLOCK

DIF0#

DIF0

^vHIBW_BYPM-LOBW#

^CKPWRGD_PD#

vOE[11:0]#

Control Logic

Resistors are integrated on 9ZXL125x devices and

external on 9ZXL123x devices

GNDA

GND x7

August 14, 2018

12 3 4 5 6 7...21

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