Datasheet > 9ZXL1550DKILFT

9ZXL1550DKILFT

更新时间： 2024-09-24 01:05:19

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
23页	292K
描述
15-Output DB1900Z Derivative for PCIe Gen1â4 and UPI

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9ZXL1550DKILFT 数据手册

15-Output DB1900Z Derivative

for PCIe Gen1–4 and UPI

9ZXL1530D / 9ZXL1550D

Datasheet

Description

Features

▪ LP-HCSL outputs; eliminate 30 resistors, save 51mm²of area

The 9ZXL1530D / 9ZXL1550D are second-generation

enhanced-performance DB1900Z-derivative differential buffers.

The parts are pin-compatible upgrades to the 9ZXL1530B and

9ZXL1550B, while offering a much improved phase jitter

performance. A fixed external feedback maintains low drift for

critical QPI/UPI applications. In fanout mode, the devices meet the

DB2000Q additive phase jitter specification.

(1530D)

▪ LP-HCSL outputs with 85Ω Zout; eliminate 60 resistors, save

103mm²of area (1550D)

▪ SMBus OE bits; software control of each output

▪ 9 selectable SMBus addresses; multiple devices can share the

same SMBus segment

▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL

PCIe Clocking Architectures

topologies

▪ Common Clocked (CC)

▪ Hardware/SMBus control of PLL bandwidth and bypass;

change mode without power cycle

▪ Independent Reference (IR) with and without spread spectrum

▪ Spread spectrum compatible; tracks spreading input clock for

EMI reduction

Typical Applications

▪ 9 × 9 mm 64-VFQFPN package; small board footprint

▪ Servers

▪ Storage

▪ Networking

▪ SSDs

Key Specifications

▪ Cycle-to-cycle jitter: < 50ps

▪ Output-to-output skew: < 50ps

▪ Input-to-output delay: fixed at 0ps

▪ Input-to-output delay variation: < 50ps

▪ Additive phase jitter: PCIe Gen4 < 53fs rms

▪ Additive phase jitter: IF-UPI < 70fs rms

▪ Additive phase jitter: DB2000Q filter < 80fs rms

Output Features

▪ 15 Low-Power HCSL (LP-HCSL) output pairs (1530D)

▪ 15 Low-Power HCSL (LP-HCSL) output pairs with 85Ω Zout

(1550D)

Block Diagram

VDDR

VDDA

VDD x3

VDDIO x4

FBOUT_NC#

FBOUT_NC

PLL

DIF_IN#

DIF_IN

DIF14#

DIF14

^100M_133M#

^SADR[1:0]_tri

SMBCLK

outputs

SMBus

Engine

Factory

Configuration

SMBDAT

DIF0#

DIF0

^vHIBW_BYPM-LOBW#

^CKPWRGD_PD#

Control Logic

Resistors are integrated on 9ZXL1550 devices

and external on 9ZXL1530 devices.

GNDA

GND x12

April 12, 2018

12 3 4 5 6 7...23

中文翻译

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