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9ZXL0651E

更新时间： 2023-12-20 18:44:10
品牌 Logo 应用领域
瑞萨 - RENESAS PC
页数 文件大小 规格书
34页 1350K
描述
6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

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9ZXL0651E 数据手册

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9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet  
Table 1. Pin Descriptions (Cont.)  
9ZXL12x1 9ZXL08x1 9ZXL06x1 9ZXL04x1  
Name  
EPAD  
Type  
Description  
Pin No.  
Pin No.  
Pin No.  
Pin No.  
GND  
Connect epad to ground.  
True half of differential feedback output. This pin should NOT  
65  
49  
41  
33  
FBOUT_NC  
Output be connected to anything outside the chip. It exists to provide  
delay path matching to get 0 propagation delay.  
16  
15  
9
8
11  
10  
9
8
Complementary half of differential feedback output. This pin  
Output should NOT be connected to anything outside the chip. It exists  
to provide delay path matching to get 0 propagation delay.  
FBOUT_NC#  
GND  
GND  
GND  
GND  
GND  
GNDA  
GNDR  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
Ground pin.  
23  
33  
41  
48  
58  
2
49  
49  
49  
49  
-
41  
41  
-
33  
n/a  
-
Ground pin.  
Ground pin.  
Ground pin.  
-
-
Ground pin.  
-
-
Ground pin for the PLL core.  
Analog ground pin for the differential input (receiver).  
49  
2
41  
4
33  
33  
7
12, 20,  
43, 45, 46  
10, 11,  
17, 30  
NC  
—
No connection.  
3
30, 40  
SMBCLK  
SMBDAT  
Input  
I/O  
Clock pin of SMBUS circuitry.  
Data pin of SMBUS circuitry.  
13  
12  
7
6
9
8
7
6
10, 15,  
19, 27,  
34, 38, 42 31, 35, 39  
12, 16, 20,  
21, 25, 29,  
12, 16,  
21, 25, 29  
VDD  
Power Power supply, nominally 3.3V.  
24  
VDD  
Power Power supply, nominally 3.3V.  
Power Power supply, nominally 3.3V.  
Power Power supply for PLL core.  
40  
57  
1
-
-
-
-
-
-
VDD  
VDDA  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
44  
-
1
-
31  
-
Power Power supply for differential outputs.  
Power Power supply for differential outputs.  
Power Power supply for differential outputs.  
Power Power supply for differential outputs.  
25  
32  
49  
56  
-
-
-
-
-
-
-
-
-
Power supply for differential input clock (receiver). This VDD  
Power should be treated as an analog power rail and filtered  
appropriately. Nominally 3.3V.  
VDDR  
8
3
11  
18  
-
5
13  
19  
-
2
15  
18  
-
Active low input for enabling output 0. This pin has an internal  
pull-down.  
vOE0#  
vOE1#  
vOE10#  
Input  
Input  
Input  
19  
20  
61  
1 = disable output, 0 = enable output.  
Active low input for enabling output 1. This pin has an internal  
pull-down.  
1 = disable output, 0 = enable output.  
Active low input for enabling output 10. This pin has an internal  
pull-down.  
1 = disable output, 0 = enable output.  
©2018-2022 Renesas Electronics Corporation  
8
December 19, 2022  
1...567891011...34

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