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9ZX21201BKLF PDF预览

9ZX21201BKLF

更新时间: 2024-02-07 17:38:40
品牌 Logo 应用领域
艾迪悌 - IDT 输出元件PC
页数 文件大小 规格书
16页 222K
描述
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI

9ZX21201BKLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN, LCC64,.35SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.41
Samacsys Description:VFQFP-N 9.0 X 9.0 X 0.9 MM - NO LEAD系列:9ZX
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N64
JESD-609代码:e3长度:9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:64实输出次数:12
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC64,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.065 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:9 mm
Base Number Matches:1

9ZX21201BKLF 数据手册

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DATASHEET  
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI  
9ZX21201  
General Description  
Features/Benefits  
The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express  
Gen3 or QPI applications. The part is backwards compatible to  
PCIe Gen1 and Gen2. A fixed external feedback maintains low drift  
for critical QPI applications. In bypass mode, the IDT9ZX21201 can  
provide outputs up to 150MHz.  
Space-saving 64-pin packages  
Fixed feedback path/ 0ps input-to-output delay  
9 Selectable SMBus Addresses/Mulitple devices can share  
the same SMBus Segment  
12 OE# pins/Hardware control of each output  
PLL or bypass mode/PLL can dejitter incoming clock  
100MHz or 133MHz PLL mode operation/supports PCIe  
and QPI applications  
Recommended Application  
12-output PCIe Gen3/ QPI differential buffer for Romley and newer  
platforms  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLL's  
Key Specifications  
Cycle-to-cycle jitter <50ps  
Output-to-output skew < 65 ps  
Input-to-output delay variation <50ps  
PCIe Gen3 phase jitter < 1.0ps RMS  
QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
Software control of PLL Bandwidth and Bypass Settings/  
PLL can dejitter incoming clock (B Rev only)  
Output Features  
12 - 0.7V differential HCSL output pairs  
Functional Block Diagram  
OE(11:0)#  
DFB_OUT  
Z-PLL  
(SS Compatible)  
DIF(11:0)  
DIF_IN  
DIF_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
SMB_A1_tri  
Logic  
SMBDAT  
SMBCLK  
IREF  
Note: Even though the feedback is fixed, DFB_OUT still needs a  
termination network for the part to function.  
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI  
1682B - 12/08/11  
1

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