Datasheet > 9FG1901HKLFT

9FG1901HKLFT

更新时间： 2024-09-17 08:11:55

品牌	Logo	应用领域
艾迪悌 - IDT		PC 时钟
页数	文件大小	规格书
18页	192K
描述
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD

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9FG1901HKLFT 数据手册

DATASHEET

9FG1901H

Frequency Gearing Clock for CPU, PCIe Gen1 & FBD

Description

Features/Benefits

Power up default is all outputs in 1:1 mode

The 9FG1901H follows the Intel DB1900G Differential Buffer

Specification. This buffer provides 19 output clocks for CPU Host

Bus, PCI-Express, or Fully Buffered DIMM applications.The outputs

are configured with two groups. Both groups, DIF_(16:0) and

DIF_(18:17) can be equal to or have a gear ratio to the input clock.

A differential CPU clock from a CK410B+ main clock generator,

such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H

can provide outputs up to 400MHz.

•

DIF_(16:0) can be “gear-shifted” from the input CPU Host

Clock

•

DIF_(18:17) can be “gear-shifted” from the input CPU Host

Clock

•

Spread spectrum compatible

Supports output clock frequencies up to 400 MHz

8 Selectable SMBus addresses

SMBus address determines PLL or Bypass mode

VDDA controlled power down mode

Key Specifications

•

DIF output cycle-to-cycle jitter < 50ps

DIF output-to-output skew across all outputs in 1:1 mode < 150ps

Functional Block Diagram

OE_17_18#

SPREAD

COMPATIBLE

PLL

GEAR

STOP

SHIFT

LOGIC

DIF(18:17)

LOGIC

OE(16:5)#,

OE_01234#

SPREAD

COMPATIBLE

PLL

GEAR

SHIFT

LOGIC

CLK_IN

STOP

DIF(16:0)

LOGIC

CLK_IN#

HIGH_BW#

FS_A_410

CONTROL

LOGIC

SMB_A0

SMB_A1

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

IREF

IDT^TMFrequency Gearing Clock for CPU, PCIe Gen1 & FBD

1386A - 02/02/10

12 3 4 5 6 7...18

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9FG1901HKLFT 替代型号

型号	品牌	替代类型	描述	数据表
9FG1901HKLF	IDT	完全替代	Frequency Gearing Clock for CPU, PCIe Gen1 & FBD

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