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9FG1901KLF-T PDF预览

9FG1901KLF-T

更新时间: 2024-11-11 19:25:59
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 233K
描述
Clock Generator, PQCC72

9FG1901KLF-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Contact ManufacturerReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.8JESD-30 代码:S-PQCC-N72
JESD-609代码:e3湿度敏感等级:3
端子数量:72最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC72,.39SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:600 mA标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

9FG1901KLF-T 数据手册

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Integrated  
Circuit  
ICS9FG1901  
Systems, Inc.  
Frequency Generator for P4CPU, PCI Express& Fully Buffered DIMM Clocks  
Functionality at Power Up (PLL Mode)  
Recommended Application:  
CLK_IN (CPU FSB)  
MHz  
DIF_(18:0)  
DB1900G: CPU Host Bus, PCI Express and Fully-Buffered  
DIMM clocking  
FS_A_4101  
MHz  
1
0
100 <= CLK_IN < 200  
200<= CLK_IN <= 400  
CLK_IN  
CLK_IN  
Features:  
Power up default is all outputs in 1:1 mode  
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for  
correct values.  
DIF_(16:0) can be “gear-shifted” from the input CPU  
Host Clock  
DIF_(18:17) can be “gear-shifted” from the input CPU  
Host Clock  
Power Down Functionality  
Spread spectrum compatible  
Supports output clock frequencies up to 400 MHz  
8 Selectable SMBus addresses  
INPUTS  
OUTPUTS  
PLL State  
VDDA/PD# CLK_IN/CLK_IN# DIF DIF#  
Running  
Hi-Z  
3.3V (NOM)  
GND  
Running  
X
ON  
OFF  
SMBus address determines PLL or Bypass mode  
VDDA controlled power down mode  
Functionality Note  
It is recommended that Byte 2, bit 6 be toggled from 1 to 0  
and back to 1, the first time VDDA is applied. This ensures  
proper initialization of the device.  
Key Specifications:  
DIF output cycle-to-cycle jitter < 50ps  
DIF (0:18) output-to-output skew < 225ps  
DIF (0:16) output-to-output skew < 100ps  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
IREF  
GNDA  
VDDA/PD#  
HIGH_BW#  
FS_A_410  
DIF_0  
1
2
3
4
5
6
7
8
9
54 OE14#  
53 DIF_13#  
52 DIF_13  
51 OE13#  
50 DIF_12#  
49 DIF_12  
48 OE12#  
DIF_0#  
DIF_1  
DIF_1#  
GND 10  
VDD 11  
DIF_2 12  
DIF_2# 13  
DIF_3 14  
DIF_3# 15  
DIF_4 16  
47  
46  
VDD  
GND  
ICS9FG1901  
45 DIF_11#  
44 DIF_11  
43 OE11#  
42 DIF_10#  
41 DIF_10  
40 OE10#  
39 DIF_9#  
38 DIF_9  
DIF_4# 17  
OE_01234# 18  
37 OE9#  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
72-pin MLF  
0962E—01/02/07  
Other names and brands may be claimed as the property of others.  

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