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9DB102AGLF PDF预览

9DB102AGLF

更新时间: 2024-10-28 20:51:07
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 223K
描述
PLL Based Clock Driver, 9DB Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20

9DB102AGLF 技术参数

生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.64系列:9DB
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G20
长度:6.5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:20实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):4.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

9DB102AGLF 数据手册

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DATASHEET  
ICS9DB102  
Two Output Differential Buffer for PCIe Gen1 & Gen2  
Description  
Features/Benefits  
The ICS9DB102 zero-delay buffer supports PCI Express  
clocking requirements. The ICS9DB102 is driven by a differential  
SRC output pair from an ICS CK410/CK505-compliant main  
clock. It attenuates jitter on the input clock and has a selectable  
PLL Band Width to maximize performance in systems with or  
without Spread-Spectrum clocking.  
CLKREQ# pin for outputs 1 and 4/output enable for Express  
Card applications  
PLL or bypass mode/PLL can dejitter incoming clock  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLLs  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
SMBus Interface/unused outputs can be disabled  
Industrial temperature range available  
Output Features  
2 - 0.7V current mode differential output pairs (HCSL)  
Key Specifications  
Cycle-to-cycle jitter < 35ps  
Output-to-output skew < 25ps  
Functional Block Diagram  
CLKREQ0#  
CLKREQ1#  
PCIEX0  
PCIEX1  
CLK_INT  
SPREAD  
COMPATIBLE  
PLL  
CLK_INC  
PLL_BW  
SMBDAT  
SMBCLK  
CONTROL  
LOGIC  
IREF  
IDTTM Two Output Differential Buffer for PCIe Gen1 & Gen2  
852 REV J 01/15/10  
1

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