9DB106BFLF

更新时间： 2024-02-04 08:11:12

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
14页	192K
描述
Six Output Differential Buffer for PCIe Gen 2

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9DB106BFLF 数据手册

DATASHEET

9DB106

Six Output Differential Buffer for PCIe Gen 2

Description

Features/Benefits

The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2

clocking requirements. The 9DB106 is driven by a differential SRC

output pair from an IDT CK410/CK505-compliant main clock

generator. It attenuates jitter on the input clock and has a selectable

PLL bandwidth to maximize performance in systems with or without

Spread-Spectrum clocking. An SMBus interface allows control of

the PLL bandwidth and bypass options, while 2 clock request

(CLKREQ#) pins make the 9DB106 suitable for Express Card

applications.

•

CLKREQ# pin for outputs 1 and 4/ supports Express Card

applications

•

PLL or bypass mode/PLL can dejitter incoming clock

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

•

Spread Spectrum Compatible/tracks spreading input clock

for low EMI

SMBus Interface/unused outputs can be disabled

Recommended Applications

6 Output Differential Buffer for PCIe Gen 2

Key Specifications

Cycle-to-cycle jitter < 50ps

•

Output-to-output skew < 50 ps

Output Features

6 - 0.7V current mode differential output pairs (HCSL)

•

Functional Block Diagram

CLKREQ1#

CLKREQ4#

PCIEX1

CLK_INT

SPREAD

COMPATIBLE

PLL

CLK_INC

PCIEX4

PCIEX(0,2,3,5)

PLL_BW

SMBDAT

SMBCLK

CONTROL

LOGIC

IREF

IDT^®Six Output Differential Buffer for PCIe Gen 2

9DB106 REV K 04/20/11

12 3 4 5 6 7...14

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