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935075440118

更新时间： 2024-11-09 20:00:51
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 82K
描述
IC ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SSOP-24, Bus Driver/Transceiver

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935075440118 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：PLASTIC, SSOP-24针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：ABT
JESD-30 代码：R-PDSO-G24长度：8.2 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：2端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：5.3 ns
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：5.3 mm
Base Number Matches：1

935075440118 数据手册

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Philips Semiconductors  
Product specification  
8-bit transceiver with 9-bit parity checker/  
generator and flag latch (3-State)  
74ABT853  
The 74ABT853 is an octal transceiver with a parity  
generator/checker and is intended for bus–oriented applications.  
FEATURES  
• Low static and dynamic power dissipation with high speed and  
high output drive  
When Output Enable A (OEA) is High, it will place the A outputs in a  
high impedance state. Output Enable B (OEB) controls the B  
outputs in the same way.  
• Open-collector ERROR output  
• Output capability: +64mA/–32mA  
• Latch-up protection exceeds 500mA per Jedec Std 17  
The parity generator creates an odd parity output (PARITY) when  
OEB is Low. When OEA is Low, the parity of the B port, including  
the PARITY input, is checked for odd parity. When an error is  
detected, the error data is sent to the input of a latch. The error data  
can then be passed, stored, cleared, or sampled depending on the  
ENABLE and CLEAR control signals.  
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
and 200 V per Machine Model  
• Power-up 3-State  
• Live insertion/extraction permitted  
If both OEA and OEB are Low, data will flow from the A bus to the B  
bus and the part is forced into an error condition which creates an  
inverted PARITY output. This error condition can be used by the  
designer for system diagnostics.  
DESCRIPTION  
The 74ABT853 high-performance BiCMOS device combines low  
static and dynamic power dissipation with high speed and high  
output drive.  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
3.4  
UNIT  
ns  
T
amb  
t
t
Propagation delay  
An to Bn or Bn to An  
PLH  
PHL  
C = 50pF; V = 5V  
L
CC  
t
t
Propagation delay  
An to PARITY  
PLH  
PHL  
C = 50pF; V = 5V  
7.4  
ns  
L
CC  
C
Input capacitance  
I/O capacitance  
V = 0V or V  
CC  
4
7
pF  
pF  
µA  
IN  
I
C
Outputs disabled; V = 0V or V  
O CC  
I/O  
I
Total supply current  
Outputs disabled; V =5.5V  
50  
CCZ  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
DWG NUMBER  
SOT222-1  
24-Pin Plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT853 N  
74ABT853 D  
74ABT853 DB  
74ABT853 PW  
74ABT853 N  
74ABT853 D  
24-Pin plastic SO  
SOT137-1  
24-Pin Plastic SSOP Type II  
24-Pin Plastic TSSOP Type I  
74ABT853 DB  
74ABT853PW DH  
SOT340-1  
SOT355-1  
PIN CONFIGURATION  
LOGIC SYMBOL  
OEA  
A0  
1
2
3
4
5
24  
23  
22  
21  
20  
V
CC  
B0  
B1  
B2  
B3  
A1  
2
3
4
5
6
7
8
9
A2  
A3  
A0 A1 A2 A3 A4 A5 A6 A7  
OEB  
14  
1
6
7
8
9
19 B4  
18 B5  
A4  
A5  
15  
10  
PARITY  
OEA  
11  
13  
CLEAR  
ERROR  
A6  
A7  
17  
16  
15  
14  
B6  
ENABLE  
B7  
B0 B1 B2 B3 B4 B5 B6 B7  
ERROR 10  
CLEAR 11  
GND 12  
PARITY  
OEB  
23 22 21 20 19 18 17 16  
13 ENABLE  
TOP VIEW  
SA00263  
SA00262  
1
1995 Sep 06  
853-1672 15702  
1234567

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