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935080610118 PDF预览

935080610118

更新时间: 2024-09-23 21:11:27
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 109K
描述
LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP-20

935080610118 技术参数

生命周期:Obsolete包装说明:SSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84其他特性:TYPICAL VOLP < 0.8V AT VCC = 3.3V, TA = 25 DEGREE C
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:7.2 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):49 ns
座面最大高度:2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

935080610118 数据手册

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74LV374  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 02 — 14 May 2009  
Product data sheet  
1. General description  
The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop  
and 3-state outputs for bus-oriented applications. A clock input (CP) and an output enable  
input (OE) are common to all flip-flops. The 74LV374 is a low-voltage Si-gate CMOS  
device and is pin and function compatible with 74HC374 and 74HCT374.  
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and  
hold times requirements on the LOW to HIGH CP transition.  
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE  
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
2. Features  
I Wide operating voltage: 1.0 V to 5.5 V  
I Optimized for low voltage applications: 1.0 V to 3.6 V  
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Common 3-state output enable input  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Ordering information  
Table 1.  
Type number Package  
Temperature range Name  
Ordering information  
Description  
Version  
74LV374N  
74LV374D  
40 °C to +125 °C  
40 °C to +125 °C  
DIP20  
SO20  
plastic dual in-line package; 20 leads (300 mil)  
SOT146-1  
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1  
74LV374DB 40 °C to +125 °C  
SSOP20 plastic shrink small outline package; 20 leads;  
body width 5.3 mm  
SOT339-1  
74LV374PW 40 °C to +125 °C  
TSSOP20 plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  

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