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935080620112 PDF预览

935080620112

更新时间: 2024-09-23 20:09:23
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
18页 111K
描述
LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP2-20

935080620112 技术参数

生命周期:Obsolete包装说明:SSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82其他特性:BROADSIDE VERSION OF 373
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:7.2 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):53 ns
座面最大高度:2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

935080620112 数据手册

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74LV573  
Octal D-type transparent latch; 3-state  
Rev. 03 — 15 April 2009  
Product data sheet  
1. General description  
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible  
with 74HC573 and 74HCT573.  
The 74LV573 consists of eight D-type transparent latches, featuring separate D-type  
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable  
(LE) input and an output enable (OE) input are common to all internal latches.  
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches  
are transparent, that is, a latch output will change each time its corresponding D-input  
changes. When LE is LOW, the latches store the information that was present at the  
D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.  
When OE is LOW, the contents of the eight latches are available at the outputs. When OE  
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the latches.  
The 74LV573 is functionally identical to the 74LV373, but has a different pin arrangement.  
2. Features  
I Wide operating voltage: 1.0 V to 5.5 V  
I Optimized for low voltage applications: 1.0 V to 3.6 V  
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
I Inputs and outputs on opposite sides of package allowing easy interface with  
microprocessors  
I Useful as input or output port for microprocessors  
I Common 3-state output enable input  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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