Datasheet > 9250BF-12T

9250BF-12T

更新时间： 2024-01-07 17:01:40

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
12页	395K
描述
Clock Generator, CMOS, PDSO56

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9250BF-12T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-30 代码：	R-PDSO-G56	JESD-609代码：	e0
湿度敏感等级：	1	端子数量：	56
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP56,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	2.5,3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
最大压摆率：	180 mA	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

9250BF-12T 数据手册

Integrated

Circuit

Systems, Inc.

ICS9250-12

Frequency Timing Generator for PENTIUM II/III Systems

General Description

Features

Generates the following system clocks:

The ICS9250-12 is a main clock synthesizer chip for

Pentium II based systems using Rambus Interface DRAMs.

This chip provides all the clocks required for such a system

when used with a Direct Rambus Clock Generator (DRCG)

chip such as the ICS9212-01, 02, 03 and a PCI buffer 9112-17.

- 4CPUclocks(2.5V,100/133MHz)

- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)

- 2CPU/2clocks(2.5V, 50/66MHz)

-3IOAPICclocks(2.5V,16.67MHz)

-4Fixedfrequency66MHzclocks(3.3V, 66MHz)

-2REFclocks(3.3V,14.318MHz)

Spread Spectrum may be enabled by driving the SPREAD#

pin active. Spread spectrum typically reduces system EMI

by 8dB to 10dB. This simplifies EMI qualification without

resorting to board design iterations or costly shielding. The

ICS9250-12 employs a proprietary closed loop design,

which tightly controls the percentage of spreading over

process and temperature variations.

-1USBclock(3.3V,48MHz)

Efficient power management through PD#, CPU_STOP#

andPCI_STOP#.

0.5% typical down spread modulation on CPU, PCI,

IOAPIC, 3V66 and CPU/2 output clocks.

The CPU/2 clocks are inputs to the DRCG.

Usesexternal14.318MHzcrystal.

Key Specification:

CPU Output Jitter: 150ps

IOAPIC Output Jitter: 250ps

CPU/2, 3V66, PCIOutputJitter:250ps

CPU(0:3)CPU/2OutputSkew:<175ps

PCI_F, PCI1:7OutputSkew:<500ps

3V66(0:3)OutputSkew<250ps

Pin Configuration

IOAPIC(0:2)OutputSkew<250ps

CPU to 3V66 (0:3) Output Offset: 0.0 - 1.5ns (CPU leads)

CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)

CPU toAPIC Output Offset 1.5 - 4.0ns (CPU leads)

Block Diagram

56-pin SSOP

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

9250-12 Rev B 2/23/00

information being relied upon by the customer is current and accurate.

12 3 4 5 6 7...12

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与9250BF-12T相关器件

型号	品牌	获取价格	描述	数据表
9250BF-16LF	IDT	获取价格	Processor Specific Clock Generator, 150MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
9250BF-16LF-T	IDT	获取价格	Processor Specific Clock Generator, 150MHz, PDSO56, 0.300 INCH, GREEN, SSOP-56
9250BF-28LF	IDT	获取价格	SSOP-56, Tube
9250BF-50LFT	IDT	获取价格	Clock Generator
9250BFI-27LF	IDT	获取价格	Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, ROHS COM
9250CF-08	IDT	获取价格	Clock Generator
9250CF-08LF	IDT	获取价格	Clock Generator
9250CF-08T	IDT	获取价格	Clock Generator
9250CF-10	IDT	获取价格	Processor Specific Clock Generator, 100MHz, PDSO56, 0.300 INCH, SSOP-56
9250CF-10LFT	IDT	获取价格	SSOP-56, Reel

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