ICS9250-08
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
Pin Configuration
VDDREF
*FS2/REF1
*PCI_STOP/REF0
GND
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
3
4
5
6
7
8
9
•
•
3 - CPUs @2.5V, up to 150MHz.
17 - SDRAM @ 3.3V, up to 150MHz.
X1
X2
VDDPCI
•
•
•
•
•
7 - PCI @3.3V
2 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
*MODE/PCICLK_F
**FS3/PCICLK0
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
Features:
•
•
Up to 150MHz frequency support
Support power management: CPU, PCI, stop and
Power down Mode form I2C programming.
•
Spread spectrum for EMI control (0 to -0.5%,
0.25%).
•
Uses external 14.318MHz crystal
Key Specifications:
SDRAM15
SDRAM14
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FS1*
•
•
•
•
CPU – CPU: <175ps
CPU – PCI: min = 1ns max = 4ns
PCI – PCI: <250ps
SDATA
SCLK
I2C
{
SDRAM - SDRAM: <500ps
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
Block Diagram
PLL2
48MHz
24MHz
Functionality
÷2
CPU
(MHz)
FS3
FS2
FS1
FS0
PCICLK (MHz)
IOAPIC_F
X1
X2
XTAL
OSC
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133
124
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
STOP
IOAPIC0
REF [1:0]
150
140
105
110
115
120
100.3
133
112
103
66.8
83.3
75
2
CPUCLK_F
CPUCLK [2:1]
PLL1
Spread
Spectrum
1
35 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.33 (CPU/2)
33.40 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
41.33 (CPU/2)
STOP
STOP
2
FS[3:0]
MODE
LATCH
PCI
CLOCK
DIVDER
PCICLK [5:0]
PCICLK_F
4
6
POR
CPU_STOP#
PCI_STOP#
SCLK
Control
Logic
Config.
Reg.
I2
C
SDRAM [15:0]
SDRAM_F
STOP
{
16
SDATA
124
BUFFERIN
0378J—05/17/05