Datasheet > 8T49N008I

8T49N008I

更新时间： 2023-12-20 18:46:25

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
39页	1539K
描述
Programmable FemtoClock? NG LVPECL/LVDS Clock Generator with 8-Outputs

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8T49N008I 数据手册

IDT8T49N008I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS

Table 3C. I C Function Descriptions

Bits

Name

Function

Sets the PLL input clock divider. The divider value has the range of 1, 2,

4 and 5. See Table 3F. Pn[1:0] bits are programmed with values to

support default configuration settings for FSEL[1:0].

Input Clock Divider Register n

(n = 0...3)

Pn[1:0]

Sets the PLL input clock prescaler value. Valid prescaler values are x0.5,

x1 or x2. See Table 3F. Set prescaler to x2 for optimum phase noise

performance. PSn[1:0] bits are programmed with values to support

default configuration settings for FSEL[1:0].

Input Prescaler Register n

(n = 0...3)

PSn(1:0)

Sets the integer feedback divider value. Based on the FemtoClock NG

VCO range, the applicable feedback dividers settings are 16 thru 250.

Please note the register value presents bits [8:1] of Mn, the LSB of Mn is

not in the register. Mn[8:1] bits are programmed with values to support

default configuration settings for FSEL[1:0].

Integer Feedback Divider

Mn[8:1]

(n = 0...3)

Sets the output divider. The output divider value can range from 2, 3, 4,

5, 6 and 8, 10, 12 to 126 (step: 2). See Table 3G for the output divider

coding. Nn[6:0] bits are programmed with values to support default

configuration settings for FSEL[1:0].

Output Divider Register n

(n = 0...3)

Nn[6:0]

Sets the FemtoClock NG PLL bandwidth by controlling the charge pump

current. See Table 3H. CPn[1:0] bits are programmed with values to

support default configuration settings for FSEL[1:0].

PLL Bandwidth Register n

(n = 0...3)

CPn[1:0]

Bypasses PLL. Output of the prescaler is routed through the output

divider N to the output fanout buffer. Programming a 1 to this bit

bypasses the PLL. Programming a 0 to this bit routes the output of the

prescaler through the PLL. BYPASSn bits are programmed with values

to support default configuration settings for FSEL[1:0].

PLL Bypass Register n

(n = 0...3)

BYPASSn

OEn[Q0]

OEn[Q1]

OEn[Q2]

OEn[Q3]

OEn[Q4]

OEn[Q5]

OEn[Q6]

OEn[Q7]

Sets the outputs to Active or High Impedance. Programming a 0 to this

bit sets the outputs to High Impedance. Programming a 1 sets the

outputs to active status. OEn[Q0], OEn[Q1], OEn[Q2], OEn[Q3],

OEn[Q4], OEn[Q5], OEn[Q6], OEn[Q7] bits are programmed with values

to support default configuration settings for FSEL[1:0].

Output Enable Register n

(n = 0...3)

LVDS_SELn[Q0]

LVDS_SELn[Q1]

LVDS_SELn[Q2]

LVDS_SELn[Q3]

LVDS_SELn[Q4]

LVDS_SELn[Q5]

LVDS_SELn[Q6]

LVDS_SELn[Q7]

Sets the differential output style to either LVDS or LVPECL interface

levels. Programming a 1 to this bit sets the output styles to LVDS levels.

Programming a 0 to this bit sets the output styles to LVPECL levels.

LVDS_SELn[Q0], LVDS_SELn[Q1], LVDS_SELn[Q2], LVDS_SELn[Q3]

LVDS_SELn[Q4], LVDS_SELn[Q5], LVDS_SELn[Q6], LVDS_SELn[Q7]

bits are programmed with values to support default configuration settings

for FSEL[1:0].

Output Style Register n

(n = 0...3)

IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014

1...3 4 567 8 9...39

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与8T49N008I相关器件

型号	品牌	获取价格	描述	数据表
8T49N012I	RENESAS	获取价格	FemtoClock? NG Crystal-to-3.3V, 2.5V LVPECL/LVCMOS Clock Generator with Fanout Buffer
8T49N028	RENESAS	获取价格	Crystal-to-3.3V, 2.5V Multiple Frequency Clock Generator with Fanout Buffer
8T49N1012	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012_18	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012-000NLGI	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012-000NLGI8	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012-001NLGI	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012-001NLGI8	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012-002NLGI	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer
8T49N1012-002NLGI8	IDT	获取价格	FemtoClock NG 12-Output Frequency Synthesizer

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