Datasheet > 8T49N008I

8T49N008I

更新时间： 2023-12-20 18:46:25

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
39页	1539K
描述
Programmable FemtoClock? NG LVPECL/LVDS Clock Generator with 8-Outputs

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8T49N008I 数据手册

IDT8T49N008I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

1, 2

Name

Q0, nQ0

Q1, nQ1

V_CCO

Type

Description

Output

Power

Output

Differential output pair. LVPECL or LVDS interface levels.

Output supply pins.

3, 4

5, 26

6, 7

Q2, nQ2

Q3, nQ3

Differential output pair. LVPECL or LVDS interface levels.

8, 9

10, 13, 18,

21, 31, 34,

37, 40

V_EE

Power

Negative supply pins.

11,

XTAL_IN

XTAL_OUT

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Crystal frequency is selected from Table 3A.

Input

CLK

Pulldown

Non-inverting differential clock input.

Pullup/

Pulldown

nCLK

Inverting differential clock input. Internal resistor bias to V_CC/2.

Frequency and configuration. Selects between one of four factory

programmable power-up default configurations. The four configurations can

have different PLL states, output frequencies, output styles and output states.

These default configurations can be overwritten after power-up via I²C.

LVCMOS/LVTTL interface levels.

00 = Configuration 0 (default)

01 = Configuration 1

10 = Configuration 2

11 = Configuration 3

16,

FSEL0,

FSEL1

Input

Pulldown

19, 38

22, 23

24, 25

27, 28

29, 30

ADDR_SEL

V_CC

Input

Power

Output

Input

I²C Address select pin. LVCMOS/LVTTL interface levels.

Core supply pins.

nQ7, Q7

nQ6, Q6

nQ5, Q5

nQ4, Q4

SCLK

Differential output pair. LVPECL or LVDS interface levels.

I²C Clock Input. LVCMOS/LVTTL interface levels.

I²C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open Drain.

Analog supply pin.

Pullup

SDATA

V_CCA

Input/Output

Power

LOCK

Output

PLL Lock Indicator. LVCMOS/LVTTL interface levels.

Input source control pin. LVCMOS/LVTTL interface levels.

0 = XTAL (default)

CLK_SEL

Input

Pulldown

1 = CLK, nCLK

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

3.5

Maximum

Units

Input Capacitance

Input Pulldown Resistor

Input Pullup Resistor

R_PULLDOWN

R_PULLUP

k

IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014

1 234 5 6 7...39

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