Datasheet > 8T49N008I

8T49N008I

更新时间： 2023-12-20 18:46:25

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
39页	1539K
描述
Programmable FemtoClock? NG LVPECL/LVDS Clock Generator with 8-Outputs

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8T49N008I 数据手册

IDT8T49N008I Data Sheet

PROGRAMMABLE FEMTOCLOCK^®NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS

Table 3D. Feedback Divider Mn Coding

Mn[8:1]

Do Not Use

00001000

00001001

00001010

00001011

00001100 thru 00011111

00100000

00100001

00100010

00100011

00100100

...

Feedback Divider Mn

1 thru 15

24 thru 62

00110010

00110011

00110100

00110101

...

100

102

104

106

01111010

01111011

01111100

01111101

244

246

248

250

Note: Mn is always an even value. The Mn[0] bits are not implemented.

Table 3E. PLL Pre-Scaler P Coding

Input Clock

Divider

Input Clock

Prescaler

Input Frequency (MHz)

CLK_SEL

Input

P[1:0]

PS[1:0]

Minimum

Maximum

x0.5

XTAL

120

240

x0.5

100

240

480

120

480

800

240

600

800

300

x0.5

CLK

x0.5

IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014

1...4 5 678 9 10...39

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