8SLVD1212 PDF预览

8SLVD1212

更新时间: 2025-09-22 14:58:07
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
19页 2110K
描述
1:12, LVDS Output Fanout Buffer

8SLVD1212 数据手册

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8SLVD1212  
Datasheet  
1:12, LVDS Output Fanout  
Features  
The 8SLVD1212 is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of high-frequency,  
very low additive phase-noise clock and data signals.  
Description  
Twelve low skew, low additive jitter LVDS output pairs  
Two selectable, differential clock input pairs  
Differential PCLK, nPCLK pairs can accept the following  
differential input levels: LVDS, LVPECL, CML  
The 8SLVD1212 is characterized to operate from a 2.5V power  
supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the device ideal for clock distribution  
applications that demand well-defined performance and  
repeatability.  
Maximum input clock frequency: 2GHz (maximum)  
LVCMOS/LVTTL interface levels for the control input select  
pins  
Output skew: 40ps (maximum)  
Two selectable differential inputs and twelve low skew outputs are  
available. The integrated bias voltage reference enables easy  
interfacing of single-ended signals to the device inputs.  
Propagation delay: 310ps (typical)  
Low additive phase jitter, RMS; fREF = 156.25MHz,  
10kHz to 20MHz: 77fs (typical)  
The 8SLVD1212 is optimized for low power consumption and low  
additive phase noise.  
Device current consumption (IDD): 213mA (maximum)  
2.5V supply voltage  
Lead-free (RoHS 6), 6 6 mm, 40-VFQFN packaging  
-40°C to 85°C ambient operating temperature  
Block Diagram  
8SLVD1212  
Q0  
nQ0  
Voltage  
Reference  
VREF0  
Q1  
nQ1  
VDD  
Q2  
nQ2  
PCLK0  
nPCLK0  
Q3  
nQ3  
Q4  
nQ4  
GND  
VDD  
fREF  
Q5  
nQ5  
PCLK1  
nPCLK1  
Q6  
nQ6  
Q7  
nQ7  
GND  
VDD  
Q8  
nQ8  
SEL  
Q9  
nQ9  
GND  
Q10  
nQ10  
Voltage  
Reference  
VREF1  
Q11  
nQ11  
©2021 Renesas Electronics Corporation  
1
February 2, 2021  

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