Datasheet > 8SLVD1212NLGI/W

8SLVD1212NLGI/W

更新时间： 2022-02-26 11:08:26

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	555K
描述
1:12, LVDS Output Fanout Buffer

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8SLVD1212NLGI/W 数据手册

1:12, LVDS Output Fanout Buffer

8SLVD1212

Datasheet

General Description

Features

The 8SLVD1212 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The 8SLVD1212 is

characterized to operate from a 2.5V power supply. Guaranteed

output-to-output and part-to-part skew characteristics make the

8SLVD1212 ideal for those clock distribution applications demanding

well-defined performance and repeatability. Two selectable

differential inputs and twelve low skew outputs are available. The

integrated bias voltage reference enables easy interfacing of

single-ended signals to the device inputs. The device is optimized for

low power consumption and low additive phase noise.

• Twelve low skew, low additive jitter LVDS output pairs

• Two selectable, differential clock input pairs

• Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL, CML

• Maximum input clock frequency: 2GHz (maximum)

• LVCMOS/LVTTL interface levels for the control input select pins

• Output skew: 45ps (max)

• Propagation delay: 310ps (typical)

• Low additive phase jitter, RMS; f_REF= 156.25MHz, 

10kHz - 20MHz: 77fs (typical)

• Maximum device current consumption (I_DD): 213mA

• 2.5V supply voltage

• Lead-free (RoHS 6), 40-Lead VFQFN packaging

• -40°C to 85°C ambient operating temperature

Pin Assignment

38 37 36 35 34 33 32 31

SEL

GND

nQ7

PCLK1

nPCLK1

VREF1

V_DD

nQ6

8SLVD1212

V_DD

nQ5

VREF0

nPCLK0

nQ4

PCLK0

GND

11 12

13 14

16 17 18 19 20

40-Lead VFQFN

6.0mm x 6.0mm x 0.9mm package body

Revision 3, July 5, 2016

12 3 4 5 6 7...21

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