Datasheet > 8SLVD2104NBGI/W

8SLVD2104NBGI/W

更新时间： 2022-02-26 11:48:56

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	436K
描述
Dual 1:4, LVDS Output Fanout Buffer

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数据手册

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8SLVD2104NBGI/W 数据手册

Dual 1:4, LVDS Output Fanout Buffer

8SLVD2104

DATA SHEET

Features

General Description

• Two 1:4, low skew, low additive jitter LVDS fanout buffers

The 8SLVD2104 is a high-performance differential dual 1:4 LVDS

fanout buffer. The device is designed for the fanout of high-frequency,

very low additive phase-noise clock and data signals. The

• Two differential clock inputs

• Differential pairs can accept the following differential input

levels: LVDS and LVPECL

8SLVD2104 is characterized to operate from a 2.5V power supply.

Guaranteed output-to-output and part-to-part skew characteristics

make the 8SLVD2104 ideal for those clock distribution applications

demanding well-defined performance and repeatability. Two

independent buffers with four low skew outputs each are available.

The integrated bias voltage generators enables easy interfacing of

single-ended signals to the device inputs. The device is optimized for

low power consumption and low additive phase noise.

• Maximum input clock frequency: 2GHz

• Output bank skew: 35ps, (maximum)

• Propagation delay: 300ps, (maximum)

• Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz): 

105fs, (maximum)

•

2.5V supply voltage

• Lead-free (RoHS 6) 28-Lead VFQFN package

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

28 27 26 25 24 23 22

GND

QB3

nQA3

20 QA3

nQB3

19 nQA2

8SLVD2104

PCLKB

QA2

nQA1

QA1

nPCLKB

VDD

VREFB

9 10 11 12 13 14

28-Lead, 5mm x 5mm VFQFN

8SLVD2104 REVISION 1 08/03/15

12 3 4 5 6 7...16

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