Datasheet > 8SLVD1212NLGI

8SLVD1212NLGI

更新时间： 2022-02-26 10:52:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	500K
描述
1:12, LVDS Output Fanout Buffer

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8SLVD1212NLGI 数据手册

8SLVD1212

Datasheet

1:12, LVDS Output Fanout Buffer

Features

Description

▪ Twelve low skew, low additive jitter LVDS output pairs

The 8SLVD1212 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency,

very low additive phase-noise clock and data signals.

▪ Two selectable, differential clock input pairs

▪ Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL, CML

The 8SLVD1212 is characterized to operate from a 2.5V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the device ideal for clock distribution

applications that demand well-defined performance and

repeatability.

▪ Maximum input clock frequency: 2GHz (maximum)

▪ LVCMOS/LVTTL interface levels for the control input select

pins

▪ Output skew: 40ps (maximum)

Two selectable differential inputs and twelve low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs.

▪ Propagation delay: 310ps (typical)

▪ Low additive phase jitter, RMS; f_REF= 156.25MHz,

10kHz to 20MHz: 77fs (typical)

The 8SLVD1212 is optimized for low power consumption and low

additive phase noise.

▪ Device current consumption (I_DD): 213mA (maximum)

▪ 2.5V supply voltage

▪ Lead-free (RoHS 6), 6 6 mm, 40-VFQFN packaging

▪ -40°C to 85°C ambient operating temperature

Block Diagram

8SLVD1212

nQ0

Voltage

Reference

V_REF0

nQ1

V_DD

nQ2

PCLK0

nPCLK0

nQ3

GND

V_DD

nQ4

f_REF

nQ5

PCLK1

nPCLK1

nQ6

nQ7

GND

V_DD

nQ8

SEL

nQ9

GND

Q10

nQ10

Voltage

Reference

V_REF1

Q11

nQ11

December 22, 2017

12 3 4 5 6 7...20

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