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89LV1632RPQK-30

更新时间： 2024-02-17 00:24:33

品牌	Logo	应用领域
麦斯威 - MAXWELL		存储内存集成电路静态存储器
页数	文件大小	规格书
12页	199K
描述
16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM

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89LV1632RPQK-30 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	QFP,
针数：	68	Reach Compliance Code：	compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.32.00.41
风险等级：	5.84	Is Samacsys：	N
最长访问时间：	30 ns	JESD-30 代码：	S-CQFP-G68
长度：	37.9476 mm	内存密度：	16777216 bit
内存集成电路类型：	SRAM MODULE	内存宽度：	32
功能数量：	1	端子数量：	68
字数：	524288 words	字数代码：	512000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	512KX32
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	6.1976 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	37.9476 mm	Base Number Matches：	1

89LV1632

16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE ⁽²⁾(OE LOW FIIXED)

F^IGURE6. TIMING WAVEFORM OF WRITE CYCLE ⁽³⁾(CS CONTROLLED)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low.

A write ends at the earliest transition CS going high or WE going high. t_WPis measured from the beginning of write to the end

of write.

3. t_CWis measured from the later of CS going low to end of write.

4. t_ASis measured from the address valid to the beginning of write.

5. t_WRis measured from the end of write to the address change. t_WRapplied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write

cycle.

8. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. D_OUTis the read data of the new address.

10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not

be applied.

08.18.05 REV 3

All data sheets are subject to change without notice

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