Datasheet > 874001AGI-02

874001AGI-02

更新时间： 2024-09-29 21:13:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	1099K
描述
PLL/Frequency Synthesis Circuit

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技术参数
数据手册

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874001AGI-02 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.86
Base Number Matches：	1

874001AGI-02 数据手册

PRELIMINARY

PCI EXPRESS/JITTER ATTENUATOR

ICS874001I-02

GENERAL DESCRIPTION

FEATURES

The ICS874001I-02 is a high performance Jitter

• One differential LVDS output pair

ICS

HiPerClockS™

Attenuator designed for use in PCI Express™ sys-

tems. In some PCI Express systems, such as those

found in desktop PCs, the PCI Express clocks are

generated from a low bandwidth, high phase noise

PLL frequency synthesizer. In these systems, a jitter

• One differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency range: 98MHz - 640MHz

• Input frequency range: 98MHz - 128MHz

• VCO range: 490MHz - 640MHz

attenuator may be required to attenuate high frequency random

and deterministic jitter components from the PLL synthesizer

and from the system board. The ICS874001I-02 has 2 PLL

bandwidth modes: 2.2MHz and 3MHz. The 2.2MHz mode will

provide maximum jitter attenuation, but with higher PLL tracking

skew and spread spectrum modulation from the motherboard

synthesizer may be attenuated. The 3MHz bandwidth provides

the best track-ing skew and will pass most spread profiles, but

the jitter attenuation will not be as good as the lower bandwidth

modes. The 874001I-02 can be set for different modes using the

F_SELx pins, as shown in Table 3C.

• Cycle-to-cycle jitter: 50ps (maximum) design target

• 3.3V or 2.5V operating supply

• Two bandwidth modes allow the system designer to make

jitter attenuation/tracking skew design trade-offs

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

The ICS874001I-02 uses IDT’s 3^rdGeneration FemtoClock^TM

PLL technology to achive the lowest possible phase noise.

The device is packaged in a small 20-pin TSSOP package,

making it ideal for use in space constrained applications such as

PCI Express add-in cards.

packages

PLL_SEL

PIN ASSIGNMENT

V^DDO

BW_SEL

F_SEL1

V^DDA

F_SEL0

GND

nCLK

CLK

PLL _SEL CONTROL TABLE

PLL BANDWIDTH CONTROL TABLE

BW_SEL

0 = Bypass

0 = PLL Bandwidth: 2.2MHz (default)

1 = PLL Bandwidth: 3MHz

1 = VCO (default)

V^DD

ICS874001I-02

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm package body

G Package

BLOCK DIAGRAM

Pullup

PLL_SEL

Pulldown

BW_SEL

0 = 2.2MHz

1 = 3MHz

Top View

Output Divider

0 0 ÷5

0 1 ÷4

1 0 ÷2 (default)

1 1 ÷1

Pulldown

CLK

Pullup

VCO

490 - 640MHz

nCLK

Phase

Detector

Internal Feedback

÷5

Pullup/Pulldown

F_SEL[1:0]

Pulldown

Pullup

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization

and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT^™/ ICS^™PCI EXPRESS/JITTER ATTENUATOR

ICS874001AGI-02 REV. A JANUARY 3, 2007

12 3 4 5 6 7...13

中文翻译

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与874001AGI-02相关器件

型号	品牌	获取价格	描述	数据表
874001AGI-02T	IDT	获取价格	PLL/Frequency Synthesis Circuit
874001AGI-05LF	IDT	获取价格	PCI EXPRESS™ JITTER ATTENUATOR
874001AGI-05LFT	IDT	获取价格	PCI EXPRESS™ JITTER ATTENUATOR
874003AG	IDT	获取价格	PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.5
874003AG-02	IDT	获取价格	PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.5
874003AG-02LF	IDT	获取价格	PCI EXPRESS Jitter Attenuator
874003AG-02LFT	IDT	获取价格	PCI EXPRESS Jitter Attenuator
874003AG-02T	IDT	获取价格	PCI EXPRESS Jitter Attenuator
874003AG-04	IDT	获取价格	PCI EXPRESS™ Jitter Attenuator
874003AG-04LF	IDT	获取价格	PCI EXPRESS™ Jitter Attenuator

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