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874003AG

更新时间： 2024-09-29 20:06:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 174K
描述
PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20

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874003AG 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.3
系列：874003输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：20
实输出次数：3最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
最小 fmax：98 MHzBase Number Matches：1

874003AG 数据手册

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ICS874003  
PCI EXPRESS  
JITTER ATTENUATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS874003 is a high performance Differential-to-LVDS  
Jitter Attenuator designed for use in PCI Express systems.  
In some PCI Express systems, such as those found in  
desktop PCs, the PCI Express clocks are generated from a  
low bandwidth, high phase noise PLL frequency  
synthesizer. In these systems, a jitter attenuator may be  
required to attenuate high frequency random and  
deterministic jitter components from the PLL synthesizer  
and from the system board. The ICS874003 has 3 PLL  
bandwidth modes: 200kHz, 400kHz, and 800kHz. The  
200kHz mode will provide maximum jitter attenuation, but  
with higher PLL tracking skew and spread spectrum  
modulation from the motherboard synthesizer may be  
attenuated.The 400kHz provides an intermediate bandwidth  
that can easily track triangular spread profiles, while  
providing good jitter attenuation. The 800kHz bandwidth  
provides the best tracking skew and will pass most spread  
profiles, but the jitter attenuation will not be as good as the  
lower bandwidth modes. Because some 2.5Gb serdes have  
x20 multipliers while others have than x25 multipliers, the  
ICS874003 can be set for 1:1 mode or 5/4 multiplication  
mode (i.e. 100MHz input/125MHz output) using the FSEL pins.  
• Three Differential LVDS output pairs  
• One Differential clock input  
• CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• Output frequency range: 98MHz - 160MHz  
• Input frequency range: 98MHz - 128MHz  
• VCO range: 490MHz - 640MHz  
• Cycle-to-cycle jitter: 35ps (maximum)  
• 3.3V operating supply  
• Three bandwidth modes allow the system designer to  
make jitter attenuation/tracking skew design trade-offs  
• 0°C to 70°C ambient operating temperature  
• Available in both standard and lead-free RoHS compliant  
packages  
PLL BANDWIDTH  
The ICS874003 uses IDT’s 3rd Generation FemtoClock®  
PLL technology to achive the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package,  
making it ideal for use in space constrained applications  
such as PCI Express add-in cards.  
BW_SEL  
0 = PLL Bandwidth: ~200kHz  
Float = PLL Bandwidth: ~400kHz (default)  
1 = PLL Bandwidth: ~800kHz  
BLOCK DIAGRAM  
Pullup  
OEA  
PIN ASSIGNMENT  
Pulldown  
F_SELA  
QA1  
VDDO  
nQA1  
VDDO  
QB0  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
2
3
4
5
6
7
8
9
QA0  
QA0  
nQA0  
MR  
Float  
BW_SEL  
nQB0  
F_SELA  
0 = ~200kHz  
Float = ~400kHz  
1 = ~800kHz  
0
1
÷5 (default)  
÷4  
F_SELB  
OEB  
GND  
nCLK  
CLK  
nQA0  
QA1  
BW_SEL  
nc  
VDDA  
F_SELA  
Pulldown  
CLK  
Phase  
Detector  
VCO  
OEA  
VDD  
nQA1  
10  
Pullup  
490 - 640MHz  
nCLK  
ICS874003  
20-LeadTSSOP  
QB0  
F_SELB  
0
1
÷5 (default)  
÷4  
6.5mm x 4.4mm x 0.92mm  
package body  
nQB0  
M = ÷5 (fixed)  
G Package  
Top View  
Pulldown  
F_SELB  
Pulldown  
Pullup  
MR  
OEB  
874003AG  
www.idt.com  
REV. A OCTOBER 5, 2010  
1
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