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874003DG-02 PDF预览

874003DG-02

更新时间: 2024-01-12 21:25:20
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 1050K
描述
PLL Based Clock Driver, 874003 Series, 3 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20

874003DG-02 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:874003输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:3最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.145 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最小 fmax:98 MHz
Base Number Matches:1

874003DG-02 数据手册

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PCI EXPRESS™ JITTER ATTENUATOR  
ICS874003-02  
GENERAL DESCRIPTION  
FEATURES  
Three Differential LVDS output pairs  
The ICS874003-02 is a high performance Dif-  
ICS  
ferential-to-LVDS Jitter Attenuator designed for  
use in PCI Express systems. In some PCI Express  
systems, such as those found in desktop PCs, the  
PCI Express clocks are generated from a low  
HiPerClockS™  
One Differential clock input  
CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
bandwidth, high phase noise PLL frequency synthesizer. In  
these systems, a jitter attenuator may be required to attenuate  
high frequency random and deterministic jitter components  
from the PLL synthesizer and from the system board. The  
ICS874003-02 has a bandwidth of 400kHz. The 400kHz  
provides an intermediate bandwidth that can easily track  
triangular spread profiles, while providing good jitter  
attenuation.  
Output frequency range: 98MHz - 320MHz  
Input frequency range: 98MHz - 128MHz  
VCO range: 490MHz - 640MHz  
Cycle-to-cycle jitter: 35ps (maximum)  
Supports PCI-Express Spread-Spectrum Clocking  
The 400kHz bandwidth mode allows the system designer to  
make jitter attenuation/tracking skew design trade-offs  
The ICS874003-02 uses IDT’s 3rd Generation FemtoClockTM  
PLL technology to achive the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express add-in cards.  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
F_SEL[2:0] FUNCTION TABLE  
Inputs  
F_SEL2 F_SEL1 F_SEL0 QA0/nQA0, QA0/nQA0 QB0/nQB0  
Outputs  
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
÷2  
÷5  
÷4  
÷2  
÷2  
÷5  
÷4  
÷4  
÷2  
÷2  
÷2  
÷4  
÷5  
÷4  
÷5  
÷4  
BLOCK DIAGRAM  
Pullup  
OEA  
3
Pulldown  
PIN ASSIGNMENT  
F_SEL2:0  
QA0  
nQA1  
VDDO  
QB0  
QA1  
VDDO  
QA0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
÷5  
÷4  
nQA0  
QA1  
÷2 (default)  
nQB0  
nQA0  
F_SEL2  
OEB  
GND  
nCLK  
CLK  
MR  
F_SEL0  
nc  
VDDA  
F_SEL1  
Pulldown  
CLK  
Phase  
Detector  
VCO  
nQA1  
Pullup  
nCLK  
490 - 640MHz  
3
OEA  
VDD  
QB0  
÷5  
÷4  
ICS874003-02  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm  
package body  
÷2 (default)  
nQB0  
M = ÷5 (fixed)  
Pulldown  
MR  
G Package  
Top View  
Pullup  
OEB  
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR  
1
ICS874003AG-02 REVA March 3, 2009  

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