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874003AGI-02T PDF预览

874003AGI-02T

更新时间: 2023-02-26 15:12:56
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
14页 1027K
描述
PLL/Frequency Synthesis Circuit, PDSO20

874003AGI-02T 数据手册

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PCI EXPRESS™ JITTER ATTENUATOR  
ICS874003I-02  
GENERAL DESCRIPTION  
FEATURES  
Three Differential LVDS output pairs  
The ICS874003I-02 is a high performance Dif-  
ICS  
ferential-to-LVDS Jitter Attenuator designed for  
use in PCI Express systems. In some PCI Express  
systems, such as those found in desktop PCs, the  
PCI Express clocks are generated from a low  
HiPerClockS™  
One Differential clock input  
CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
bandwidth, high phase noise PLL frequency synthesizer. In  
these systems, a jitter attenuator may be required to attenuate  
high frequency random and deterministic jitter components  
from the PLL synthesizer and from the system board. The  
ICS874003I-02 has a bandwidth of 400kHz. The 400kHz  
provides an intermediate bandwidth that can easily track  
triangular spread profiles, while providing good jitter  
attenuation.  
Output frequency range: 98MHz - 320MHz  
Input frequency range: 98MHz - 128MHz  
VCO range: 490MHz - 640MHz  
Cycle-to-cycle jitter: 35ps (maximum)  
Supports PCI-Express Spread-Spectrum Clocking  
The 400kHz bandwidth mode allows the system designer to  
make jitter attenuation/tracking skew design trade-offs  
The ICS874003I-02 uses IDT’s 3rd Generation FemtoClockTM  
PLL technology to achive the lowest possible phase noise.  
The device is packaged in a 20 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express add-in cards.  
3.3V operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
F_SEL[2:0] FUNCTION TABLE  
Inputs  
F_SEL2 F_SEL1 F_SEL0 QA0/nQA0, QA0/nQA0 QB0/nQB0  
Outputs  
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
÷2  
÷5  
÷4  
÷2  
÷2  
÷5  
÷4  
÷4  
÷2  
÷2  
÷2  
÷4  
÷5  
÷4  
÷5  
÷4  
BLOCK DIAGRAM  
Pullup  
OEA  
3
PIN ASSIGNMENT  
Pulldown  
F_SEL2:0  
QA0  
nQA1  
VDDO  
QB0  
QA1  
VDDO  
QA0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
÷5  
÷4  
nQA0  
QA1  
÷2 (default)  
nQB0  
nQA0  
F_SEL2  
OEB  
GND  
nCLK  
CLK  
MR  
F_SEL0  
nc  
VDDA  
F_SEL1  
Pulldown  
Pullup  
CLK  
Phase  
Detector  
VCO  
nQA1  
490 - 640MHz  
nCLK  
3
OEA  
VDD  
QB0  
ICS874003I-02  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm  
package body  
÷5  
÷4  
÷2 (default)  
nQB0  
M = ÷5 (fixed)  
G Package  
Pulldown  
MR  
Top View  
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR  
1
ICS874003AGI-02 REV A SEPTEMBER 18, 2006  

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