PRELIMINARY
PCI EXPRESS/JITTER ATTENUATOR
ICS874001I-02
GENERAL DESCRIPTION
FEATURES
The ICS874001I-02 is a high performance Jitter
• One differential LVDS output pair
ICS
HiPerClockS™
Attenuator designed for use in PCI Express™ sys-
tems. In some PCI Express systems, such as those
found in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise
PLL frequency synthesizer. In these systems, a jitter
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 640MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874001I-02 has 2 PLL
bandwidth modes: 2.2MHz and 3MHz. The 2.2MHz mode will
provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 3MHz bandwidth provides
the best track-ing skew and will pass most spread profiles, but
the jitter attenuation will not be as good as the lower bandwidth
modes. The 874001I-02 can be set for different modes using the
F_SELx pins, as shown in Table 3C.
• Cycle-to-cycle jitter: 50ps (maximum) design target
• 3.3V or 2.5V operating supply
• Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
The ICS874001I-02 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a small 20-pin TSSOP package,
making it ideal for use in space constrained applications such as
PCI Express add-in cards.
packages
nc
PLL_SEL
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PIN ASSIGNMENT
nc
nc
nc
VDDO
Q
nQ
MR
BW_SEL
F_SEL1
VDDA
F_SEL0
nc
nc
GND
nCLK
CLK
OE
PLL _SEL CONTROL TABLE
PLL BANDWIDTH CONTROL TABLE
BW_SEL
0 = Bypass
0 = PLL Bandwidth: 2.2MHz (default)
1 = PLL Bandwidth: 3MHz
1 = VCO (default)
VDD
ICS874001I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
BLOCK DIAGRAM
Pullup
PLL_SEL
Pulldown
BW_SEL
0 = 2.2MHz
1 = 3MHz
Top View
0
1
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
Q
Pulldown
CLK
nQ
Pullup
VCO
490 - 640MHz
nCLK
Phase
Detector
Internal Feedback
÷5
2
Pullup/Pulldown
F_SEL[1:0]
MR
Pulldown
Pullup
OE
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR
1
ICS874001AGI-02 REV. A JANUARY 3, 2007