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87004AGI PDF预览

87004AGI

更新时间: 2024-11-05 21:10:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 759K
描述
PLL Based Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24

87004AGI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.16
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:87004
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:7.8 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):225
电源:2.5/3.3 VProp。Delay @ Nom-Sup:6.9 ns
传播延迟(tpd):6.7 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.045 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:15.625 MHzBase Number Matches:1

87004AGI 数据手册

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1:4, Differential-to-LVCMOS/LVTTL  
Zero Delay Clock Generator  
ICS87004I  
DATA SHEET  
General Description  
Features  
The ICS87004I is a highly versatile 1:4 Differential-  
to-LVCMOS/LVTTL Clock Generator. The ICS87004I  
has two selectable clock inputs. The CLK0, nCLK0  
and CLK1, nCLK1 pairs can accept most standard  
differential input levels. Internal bias on the nCLK0 and  
Four LVCMOS/LVTTL outputs, 7typical output impedance  
Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs  
S
IC  
HiPerClockS™  
CLKx/nCLKx pairs can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL  
nCLK1 inputs allows the CLK0 and CLK1 inputs to accept  
LVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and can  
be configured as a zero delay buffer, multiplier or divider and has an  
input and output frequency range of 15.625MHz to 250MHz. The  
reference divider, feedback divider and output divider are each  
programmable, thereby allowing for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external  
feedback allows the device to achieve “zero delay” between the input  
clock and the output clocks. The PLL_SEL pin can be used to  
bypass the PLL for system test and debug purposes. In bypass  
mode, the reference clock is routed around the PLL and into the  
internal output dividers.  
levels on CLK0 and CLK1 inputs  
Output frequency range: 15.625MHz to 250MHz  
Input frequency range: 15.625MHz to 250MHz  
VCO range: 250MHz to 500MHz  
External feedback for “zero delay” clock regeneration with  
configurable frequencies  
Programmable dividers allow for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8  
Fully integrated PLL  
Cycle-to-cycle jitter: 45ps (maximum)  
Output skew: 65ps (maximum)  
Static phase offset: 50ps 150ps (3.3V 5ꢀ), CLK0/nCLK0  
Full 3.3V or 2.5V output operating supply  
5V tolerant  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Block Diagram  
PLL_SEL  
Pin Assignment  
Pullup  
1
2
24  
23  
Q1  
GND  
Q0  
VDDO  
÷2, ÷4, ÷8, ÷16  
÷32, ÷64, ÷128  
V
SEL0  
SEL1  
SEL2  
SEL3  
DDO  
3
4
22  
21  
Q2  
GND  
Q0  
Q1  
Q2  
Q3  
0
1
Pulldown  
Pullup/Pulldown  
CLK0  
nCLK0  
0
1
5
6
7
20  
19  
18  
17  
Q3  
VDDO  
MR  
Pulldown  
Pullup/Pulldown  
CLK1  
nCLK1  
PLL  
8
FB_IN  
CLK_SEL  
9
PLL_SEL  
CLK1  
nCLK1  
V
DD  
16  
15  
14  
13  
Pulldown  
Pulldown  
CLK0  
nCLK0  
GND  
10  
11  
12  
CLK_SEL  
FB_IN  
8:1, 4:1, 2:1, 1:1,  
1:2, 1:4, 1:8  
V
DDA  
ICS87004I  
24-Lead TSSOP  
7.8mm x 4.4mm x 0.925mm package body  
G Package  
Pulldown  
SEL0  
SEL1  
SEL2  
SEL3  
MR  
Top View  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
ICS87004AGI REVISION D JANUARY 4, 2010  
1
©2009 Integrated Device Technology, Inc.  

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