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853S54AKILFT PDF预览

853S54AKILFT

更新时间: 2024-01-14 10:43:25
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
21页 322K
描述
Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer

853S54AKILFT 数据手册

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ICS853S54I Data Sheet  
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase  
noise is defined as the ratio of the noise power present in a 1Hz band  
at a specified offset from the fundamental frequency to the power  
value of the fundamental. This ratio is expressed in decibels (dBm)  
or a ratio of the power in the 1Hz band to the power in the  
fundamental. When the required offset is specified, the phase noise  
is called a dBc value, which simply means dBm at a specified offset  
from the fundamental. By investigating jitter in the frequency domain,  
we get a better understanding of its effects on the desired application  
over the entire time record of the signal. It is mathematically possible  
to calculate an expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 622.08MHz  
12kHz to 20MHz = 0.035ps (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements has  
issues relating to the limitations of the equipment. Often the noise  
floor of the equipment is higher than the noise floor of the device.  
This is illustrated above. The device meets the noise floor of what is  
shown, but can actually be lower. The phase noise is dependent on  
the input source and measurement equipment.  
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal  
Generator as external input to an Agilent 8133A 3GHz Pulse  
Generator”.  
ICS853S54AKI May 27, 2017  
5
©2017 Integrated Device Technology, Inc.  

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