Datasheet > 853S54AKILFT

853S54AKILFT

更新时间： 2024-01-29 00:06:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	322K
描述
Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer

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853S54AKILFT 数据手册

ICS853S54I Data Sheet

DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V_CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V_CC= 3.3V, V_REF should be 1.25V and

V_CC

Single Ended Clock Input

R2/R1 = 0.609.

CLKx

V_REF

nCLKx

0.1u

Figure 1. Single-Ended Signal Driving Differential Input

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

LVPECL Outputs

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1k resistor

can be used.

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

PCLK/nPCLK Inputs

For applications not requiring the use of the differential input, both

PCLK and nPCLK can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from PCLK to

ground.

ICS853S54AKI May 27, 2017

1...4 5 678 9 10...21

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853S54AKILFT 替代型号

型号	品牌	替代类型	描述	数据表
853S54AKILF	IDT	类似代替	Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer

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