ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
Name
Type
Description
QB0, nQB0
QB1, nQB1
PCLKB
Output
Output
Input
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Non-inverting LVPECL/ECL differential clock input.
3, 4
5
Pulldown
Pullup/
Pulldown
6
nPCLKB
Input
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Clock select pin for QBx outputs. When HIGH, selects QB1/nQB1 outputs.
When LOW, selects QB0/nQB0 outputs. LVCMOS/LVTTL interface levels.
7
8
CLK_SELB
VEE
Input
Power
Input
Input
Input
Pulldown
Negative supply pin.
Pullup/
Pulldown
9
nPCLKA1
PCLKA1
nPCLKA0
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
10
11
Pulldown
Pullup/
Pulldown
12
13
PCLKA0
VCC
Input
Pulldown
Non-inverting LVPECL/ECL differential clock input.
Positive supply pin.
Power
Clock select pin for QA output. When HIGH, selects QA output. When LOW,
selects nQA output. LVCMOS/LVTTL interface levels.
14
CLK_SELA
nQA, QA
Input
Pulldown
15, 16
Output
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
2
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
RPullup/Pulldown Resistor
RPULLDOWN
RVCC/2
37.5
37.5
k
k
Function Tables
Table 3A. Control Input Function Table, (Bank A)
Table 3B. Control Input Function Table, (Bank B)
Bank A
Bank B
Control Input
CLK_SELA
0 (default)
1
Outputs
Control Input Outputs
QA, nQA
CLK_SELB
0 (default)
1
QB0, nQB0
QB1, nQB1
Selects PCLKA0, nPCLKA0
Selects PCLKA1, nPCLKA1
Follows PCLKB input
Logic Low
Logic Low
Follows PCLKB input
ICS853S54AKI May 27, 2017
2
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