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844002AG-01

更新时间： 2024-01-10 01:59:53

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	1141K
描述
FEMTOCLOCKS⑩ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER

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844002AG-01 数据手册

ICS844002-01

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

Table 1. Pin Descriptions

Number

1, 7

Name

Type

Description

Unused

Power

No connect.

2, 20

3, 4

V_DDO

Q0, Q0

Output supply pins.

Output

Differential output pair. LVDS interface levels.

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs Qx to go high.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels.

Input

Pulldown

Selects between the PLL and REF_CLK as input to the dividers. When LOW,

PLL_SEL

V_DDA

Input

Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL

Bypass). LVCMOS/LVTTL interface levels.

Power

Input

Analog supply pin.

FSEL0,

F_SEL1

Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.

Core supply pins.

V_DD

Power

Input

12,

XTAL_OUT

XTAL_IN

Parallel resonant crystal interface. XTAL_OUT is the output,

XTAL_IN is the input.

REF_CLK

Input

Pulldown Non-inverting differential clock input.

Selects between crystal or REF_CLK inputs as the PLL Reference source.

Pulldown Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.

LVCMOS/LVTTL interface levels.

XTAL_SEL

Unused

Power

No connect.

GND

Power supply ground.

18, 19

Q1, Q1

Output

Differential output pair. LVDS interface levels.

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C_IN

Input Capacitance

R_PULLDOWNInput Pulldown Resistor

kΩ

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER

ICS844002AG-01 REV. A SEPTEMBER 28, 2007

123 4 5 6 7...15

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