Datasheet > 84330BYT

84330BYT

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	247K
描述
Clock Generator, PQFP32

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84330BYT 数据手册

ICS84330

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated

Circuit

Systems, Inc.

JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT

If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the

jitter performance can be improved by reducing the amplitude

swing and slowing down the edge rate. Figure 4A shows an

amplitude reduction approach for a long trace. The swing will

be approximately 0.85V for logic low and 2.5V for logic high

(instead of 0V to 3.3V). Figure 4B shows amplitude reduction

approach for a short trace. The circuit shown in Figure 4C

reduces amplitude swing and also slows down the edge rate

by increasing the resistor value.

VDD

100

Zo = 50 Ohm

Ro ~ 7 Ohm

VDD

GND

100

TEST_CLK

FREF_EXT

Driver_LVCMOS

FIGURE 4A. AMPLITUDE REDUCTION FOR A LONGTRACE

VDD

200

Ro ~ 7 Ohm

VDD

GND

100

200

TEST_CLK

FREF_EXT

Driver_LVCMOS

FIGURE 4B. AMPLITUDE REDUCTION FOR A SHORTT RACE

VDD

400

Ro ~ 7 Ohm

VDD

GND

200

400

TEST_CLK

FREF_EXT

Driver_LVCMOS

FIGURE 4C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE

84330BV

www.icst.com/products/hiperclocks.html

REV.C MAY 16, 2006

1...6 7 8910 11 12...19

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