PRELIMINARY
ICS8430BI-71
Integrated
Circuit
Systems, Inc.
700MHZ, LOW JITTER, CRYSTAL INTERFACE/
LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal.Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
fxtal
16
follows:
x 2M
fVCO =
The ICS8430BI-71 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector.With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table.Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 125 ≤ M ≤ 350.The frequency
fVCO fxtal 2M
out is defined as follows:
fout
x
=
=
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW.The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 andT0.The internal registers T0 andT1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjust-
ing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock.The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430BI-71 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW.The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hardwired to set the M divider and N output divider to a
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data clocked into register
Output of M divider
CMOS Fout
SERIAL LOADING
S_CLOCK
T1
T0
N2
N1
N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
S_DATA
S_LOAD
nP_LOAD
t
t
H
S
t
S
PARALLEL LOADING
M, N
M0:M8, N0:N2
nP_LOAD
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
www.icst.com/products/hiperclocks.html
8430BYI-71
REV.A FEBRUARY 17, 2006
2
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