Datasheet > 8430BYI-71T

8430BYI-71T

更新时间： 2024-01-21 23:54:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	167K
描述
PLL/Frequency Synthesis Circuit

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技术参数
数据手册

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8430BYI-71T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

8430BYI-71T 数据手册

PRELIMINARY

ICS8430BI-71

Integrated

Circuit

Systems, Inc.

700MHZ, LOW JITTER, CRYSTAL INTERFACE/

LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

TABLE 5. INPUT CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

TEST_CLK; NOTE 1

MHz

XTAL_IN, XTAL_OUT;

NOTE 1

f_IN

Input Frequency

MHz

S_CLOCK

MHz

t_{r_input}

Input Rise Time TEST_CLK

NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the

250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.

Using the maximum frequency of 27MHz, valid values of M are 75 ≤ M ≤ 207.

TABLE 6. CRYSTAL CHARACTERISTICS

Parameter

Test Conditions

Minimum Typical Maximum

Units

Mode of Oscillation

Frequency

Fundamental

MHz

Equivalent Series Resistance (ESR)

Shunt Capacitance

Drive Level

TABLE 7. AC CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5%, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

F_MAX

Output Frequency

700

MHz

fOUT > 87.5MHz

fOUT < 87.5MHz

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 1, 3

tjit(per)

tsk(o)

t_R/ t_F

Period Jitter, RMS; NOTE 1

Output Skew; NOTE 2, 3

Output Rise/Fall Time

9.5

20% to 80%

200

700

M, N to nP_LOAD

t_S

Setup Time

Hold Time

S_DATA to S_CLOCK

S_CLOCK to S_LOAD

M, N to nP_LOAD

t_H

S_DATA to S_CLOCK

S_CLOCK to S_LOAD

N ≠ 1

odc

Output Duty Cycle

PLL Lock Time

N = 1

t_LOCK

See Parameter Measurement Information section.

NOTE 1: Jitter performance using XTAL inputs.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

8430BYI-71

www.icst.com/products/hiperclocks.html

REV.A FEBRUARY 17, 2006

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