ICS8430-71
Integrated
Circuit
Systems, Inc.
700MH
Z, LOW
J
ITTER, CRYSTAL
I
NTERFACE
/
LVCMOS-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
250
252
254
256
•
125
126
127
128
•
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
FOUT0, nFOUT0 Output Frequency
(MHz)
Inputs
N Divider Value
N2
0
N1
0
N0
0
Minimum
125
Maximum
350
2
4
0
0
1
62.5
175
0
1
0
8
31.25
15.625
250
87.5
0
1
1
16
1
43.75
700
1
0
0
1
0
1
2
125
350
1
1
0
4
62.5
175
1
1
1
8
31.25
87.5
8430AY-71
www.icst.com/products/hiperclocks.html
REV. B JANUARY 27, 2005
4