ICS8430-71
Integrated
Circuit
Systems, Inc.
700MH
Z, LOW
J
ITTER, CRYSTAL
I
NTERFACE
/
LVCMOS-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
1, 2, 3,
28, 29, 30
31, 32
M5, M6, M7,
M0, M1, M2,
M3, M4
Input
M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
4
5, 6
7
M8
N0, N1
N2
Input
Input
Input
Power
Pullup
Pulldown
Pullup
Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core power supply pin.
9
TEST
Output
Power
Output
Power
Output
10
VCC
FOUT1,
nFOUT1
VCCO
FOUT0,
nFOUT0
11, 12
13
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
14, 15
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master reset. When logic HIGH, the internal dividers are
reset causing the true outputs (FOUTx) to go low and the inverted
17
MR
Input
Pulldown outputs (nFOUTx) to go high. When Logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Selects between the crystal oscillator or test clock as the
22
XTAL_SEL
Input
Pullup
PLL reference source. Selects XTAL inputs when HIGH.
Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS interface levels.
24, 25
XTAL1, XTAL2
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into the M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
8430AY-71
www.icst.com/products/hiperclocks.html
REV. B JANUARY 27, 2005
3
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