Datasheet > 841N254B_18

841N254B_18

更新时间： 2024-09-18 01:10:55

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
25页	542K
描述
FemtoClock NG Crystal-to-LVDS/ HCSL Clock Synthesizer

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841N254B_18 数据手册

FemtoClock NG Crystal-to-LVDS/

841N254B

Datasheet

HCSL Clock Synthesizer

Description

Features

▪ Fourth generation FemtoClock^®(NG) technology

The 841N254B is a 4-output clock synthesizer designed for S-RIO

1.3 and 2.0 reference clock applications. The device generates

four copies of a selectable 250MHz, 156.25MHz, 125MHz or

100MHz clock signal with excellent phase jitter performance. The

four outputs are organized in two banks of two LVDS and two

HCSL ouputs. The device uses IDT’s fourth generation

FemtoClock^®NG technology for an optimum of high clock

frequency and low phase noise performance, combined with a low

power consumption and high power supply noise rejection. The

synthesized clock frequency and the phase-noise performance

are optimized for driving RIO 1.3 and 2.0 SerDes reference

clocks.

▪ Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output

clock synthesized from a 25MHz fundamental mode crystal

▪ Four differential clock outputs (two LVDS and two HCSL

outputs)

▪ Crystal interface designed for 25MHz,

parallel resonant crystal

▪ RMS phase jitter at 156.25MHz, using a 25MHz crystal

(1MHz - 20MHz): 0.27ps (typical)

▪ RMS phase jitter at 156.25MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.32ps (typical)

▪ Power supply noise rejection PSNR: -50dB (typical)

▪ LVCMOS interface levels for the frequency select input

▪ Full 3.3V or 2.5V supply voltage

The device supports 3.3V and 2.5V voltage supplies and is

packaged in a small 32-lead VFQFN package. The extended

temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements.

▪ Lead-free (RoHS 6) packaging

▪ -40°C to 85°C ambient operating temperature

Function Table

Inputs

Output Frequency with

F_SEL1

F_SEL0

= 25MHz

XTAL

0 (default)

156.25MHz

125MHz

100MHz

250MHz

NOTE: F_SEL[1:0] are asynchronous controls.

Block Diagram

April 17, 2018

12 3 4 5 6 7...25

中文翻译

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