Datasheet > 841S02I

841S02I

更新时间： 2023-12-20 18:45:38

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
18页	471K
描述
PCI Express? Clock Generator

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841S02I 数据手册

PCI ExpressTM Clock Generator

841S02

DATA SHEET

General Description

Features

The 841S02 is a PLL-based clock generator specifically designed for

PCI_Express™ Clock Generation applications. This device

generates a 100MHz HCSL clock. The device offers a HCSL (Host

Clock Signal Level) clock output from a clock input reference of

25MHz. The input reference may be derived from an external source

or by the addition of a 25MHz crystal to the on-chip crystal oscillator.

An external reference may be applied to the XTAL_IN pin with the

XTAL_OUT pin left floating.

• Two 0.7V current mode differential HCSL output pairs

• Crystal oscillator interface: 25MHz

• Output frequency: 100MHz

• RMS period jitter: 3ps (maximum)

• Output skew: 35ps (maximum)

• Cycle-to-cycle jitter: 35ps (maximum)

• I²C support with readback capabilities up to 400kHz

• Spread Spectrum for electromagnetic interference (EMI) reduction

• 3.3V operating supply mode

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

The device offers spread spectrum clock output for reduced EMI

applications. An I²C bus interface is used to enable or disable spread

spectrum operation as well as select either a down spread value of

-0.35% or -0.5%.

Block Diagram

Pin Assignment

25MHz

V_SS

V^DD

19 SDATA

XTAL_IN

SRCT[1:2]

SRCC[1:2]

V_DD

SRCT2

SRCC2

Divider

Network

OSC

PLL

SCLK

XTAL_OUT

SDATA

SRCT1

SRCC1

V_SS

16 XTAL_OUT

15 XTAL_IN

Pullup

V^DD

I²C

Logic

V_DD

V_SS

IREF

V^SS

SCLK

VDDA

VSS

IREF

841S02

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm package body

G Package

Top View

841S02 Rev A 11/16/15

12 3 4 5 6 7...18

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