82C82
CMOS Octal Latching Bus Driver
March 1997
Features
Description
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
Ordering Information
• Single 5V Power Supply
PART NUMBER TEMP. RANGE
PACKAGE
PKG. NO.
o
o
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
CP82C82
IP82C82
0 C to +70 C 20 Ld PDIP
E20.3
o
o
-40 C to +85 C
• Operating Temperature Ranges
o
o
o
o
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C
CS82C82
IS82C82
0 C to +70 C 20 Ld PLCC
N20.35
o
o
o
o
-40 C to +85 C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
CD82C82
ID82C82
0 C to +70 C 20 Ld CERDIP F20.3
o
o
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
-40 C to +85 C
o
o
MD82C82/B
8406701RA
MR82C82/B
84067012A
-55 C to +125 C
SMD #
o
o
-55 C to +125 C 20 Pad CLCC J20.A
SMD #
Pinouts
82C82 (PDIP, CERDIP)
82C82 (PLCC, CLCC)
TOP VIEW
TOP VIEW
TRUTH TABLE
STB
X
OE
H
L
DI
X
L
DO
Hi-Z
L
3
2
1
20 19
H
1
2
3
4
5
6
7
8
9
V
CC
20
19
DI
DI
DI
DI
DI
DI
0
1
2
3
4
5
H
L
H
X
H
DO
0
1
2
3
4
5
6
4
5
6
7
8
18 DO
DI
DI
DI
DI
DI
3
4
5
6
7
1
2
3
4
5
↓
L
†
18 DO
17 DO
16 DO
15 DO
14 DO
13 DO
H
L
X
†
= Logic One
= Logic Zero
= Don’t Care
= Latched to Value of Last
Data
17
16
15
DO
DO
DO
Hi-Z = High Impedance
DI
DI
6
7
14 DO
↓
= Neg. Transition
PIN NAMES
12
OE
DO
7
9
10 11 12 13
PIN
DESCRIPTION
GND 10
11 STB
DI -DI
Data Input Pins
0
7
DO -DO
0
Data Output Pins
Active High Strobe
7
STB
OE
Active Low Output
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2975.1
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