82C83H
CMOS Octal Latching Inverting Bus Driver
March 1997
Features
Description
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
Ordering Information
• Low Power Operation
PART NO.
CP82C83H
IP82C83H
PACKAGE
TEMP RANGE
PKG. NO
E20.3
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
o
o
20 Ld PDIP
0 C to +70 C
o
o
-40 C to +85 C
E20.3
o
o
o
o
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C
CS82C83H
IS82C83H
20 Ld PLCC
0 C to +70 C
N20.35
N20.35
F20.3
o
o
o
o
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
-40 C to +85 C
o
o
o
o
CD82C83H
ID82C83H
20 Ld CERDIP
0 C to +70 C
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
-40 C to +85 C
F20.3
o
o
MD82C83H/B
8406702RA
0 C to +70 C
F20.3
o
o
SMD#
-55 C to +125 C F20.3
o
o
MR82C83H/B 20 Pad CLCC
-55 C to +125 C J20.A
o
o
84067022A
SMD#
-55 C to +125 C J20.A
Pinouts
82C83H (PDIP, CERDIP)
82C83H (PLCC, CLCC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
CC
DI
DI
DI
DI
DI
DI
DI
DI
20
19
0
1
2
3
4
5
3
2
1
20
19
DO
0
1
2
3
4
5
6
18 DO
17 DO
16 DO
15 DO
14 DO
13 DO
4
5
6
7
8
18 DO
DI
DI
DI
DI
DI
3
4
5
6
7
1
2
3
4
5
17
16
15
DO
DO
DO
6
7
14 DO
12
OE
DO
7
GND 10
11 STB
9
10
11 12 13
TRUTH TABLE
PIN NAMES
DESCRIPTION
STB
X
OE
DI
X
L
DO
HI-Z
H
PIN
H
L
L
L
DI - DI
Data Input Pins
0
7
H
DO - DO
0
Data Output Pins
7
H
H
X
L
STB
OE
Active High Strobe
↓
†
Active Low Output Enable
H = Logic One
L = Logic Zero
X = Don‘t Care
HI-Z = High Impedance
↓
†
= Negative Transition
= Latched to Value of Last
Data
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2971.1
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