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8407201RAS2035 PDF预览

8407201RAS2035

更新时间： 2024-10-01 14:48:19
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
10页 154K
描述
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, 0.300 INCH, CERAMIC, DIP-20

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8407201RAS2035 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：0.300 INCH, CERAMIC, DIP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.1Is Samacsys：N
系列：HC/UHJESD-30 代码：R-GDIP-T20
长度：24.195 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：335 ns认证状态：Not Qualified
筛选级别：MIL-STD-883座面最大高度：5.08 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

8407201RAS2035 数据手册

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SN54HC373, SN74HC373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS140B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC373 . . . J OR W PACKAGE  
SN74HC373 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
Eight High-Current Latches in a Single  
Package  
High-Current 3-State True Outputs Can  
Drive up to 15 LSTTL Loads  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Full Parallel Access for Loading  
Package Options Include Plastic  
17 7D  
16 7Q  
15 6Q  
14 6D  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
13  
5D  
12 5Q  
11 LE  
description  
GND 10  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
SN54HC373 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
The eight latches of the ’HC373 are transparent  
D-type latches. While the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the levels that were set up at the D inputs.  
17  
16  
15 6Q  
14  
9 10 11 12 13  
6D  
An output-enable (OE) input places the eight  
outputs in either a normal logic state (high or low  
logic levels) or the high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are off.  
The SN54HC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC373 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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