Datasheet > 83940DY-01LF

83940DY-01LF

更新时间： 2022-02-26 11:59:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	190K
描述
Low Skew, 1-to-18 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer

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数据手册

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83940DY-01LF 数据手册

Low Skew, 1-to-18

LVPECL-TO-LVCMOS / LVTTL Fanout Buffer

83940-01

DATASHEET

FEATURES

GENERAL DESCRIPTION

• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance

• Selectable LVCMOS_CLK or LVPECL clock inputs

The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL

Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The

PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels.The

single ended clock input accepts LVCMOS or LVTTL input levels.The low

impedance LVCMOS/LVTTL outputs are designed

to drive 50Ω series or parallel terminated transmis-

sion lines. The effective fanout can be increased from 18 to

36 by utilizing the ability of the outputs to drive two series

terminated lines.

• LVCMOS_CLK supports the following input types:

LVCMOS or LVTTL

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• Maximum output frequency: 250MHz

• Output skew: 85ps (maximum)

The ICS83940-01 is characterized at full 3.3V, full 2.5V

a n d m i xe d 3 . 3 V i n p u t a n d 2 . 5 V o u t p u t o p e r a t -

ing supply modes. Guaranteed output and part-to-part skew

characteristics make the ICS83940-01 ideal for those clock

distr ibution applications demanding well defined

performance and repeatability.

• Part-to-part skew: 750ps (maximum)

• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes

• 0°C to 70°C ambient operating temperature

• Available in lead-free RoHS compliant package

BLOCK DIAGRAM

PIN ASSIGNMENT

32 31 30 29 28 27 26 25

GND

CLK_SEL

PCLK

LVCMOS_CLK

CLK_SEL

PCLK

nPCLK

V^DDO

Q0:Q17

ICS83940-01

LVCMOS_CLK

Q10

Q11

GND

nPCLK

V^DD

VDDO

10 11 12 13 14 15 16

32-Lead LQFP

Y Pacakge

7mm x 7mm x 1.4mm package body

Top View

83940-01 REVISION A NOVEMBER 4, 2014

12 3 4 5 6 7...15

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