83948I
Low Skew, 1-to-12 Differential-to-
LVCMOS/LVTTL Fanout Buffer
Datasheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
Features
The 83948I is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL
Fanout Buffer and a member of the family of High Performance
Clock Solutions from IDT. The 83948I has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
• Twelve LVCMOS/LVTTL outputs
• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock
input
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
• Maximum output frequency: 250MHz
• Output skew: 350ps (maximum)
• Part-to-part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For drop in replacement part use 83948i-147
The 83948I is characterized at full 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make the
83948I ideal for those clock distribution applications demanding
well defined performance and repeatability.
Pin Assignment
Pullup
CLK_EN
D
Q
32 31 30 29 28 27 26 25
Pullup
LVCMOS_CLK
1
1
2
3
4
5
6
7
8
CLK_SEL
GND
24
23
22
21
20
Q0
Pullup
CLK
nCLK
LVCMOS_CLK
CLK
Q4
0
Pulldown
Q1
VDDO
Q5
Pullup
CLK_SEL
Q2
nCLK
CLK_EN
GND
Q3
OE
VDD
Q6
Block Diagram
19
18
17
Q4
VDDO
Q7
GND
Q5
9
10 11 12 13 14 15 16
Q6
Q7
83948I
Q8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q9
Y Package
Top View
Q10
Q11
Pullup
OE
©2016 Integrated Device Technology, Inc
1
May 19, 2016