Datasheet > 83948I-147

83948I-147

更新时间： 2024-02-19 10:35:52

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	361K
描述
Low Skew, 1-to-1 Differential to-

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83948I-147 数据手册

Low Skew, 1-to-1 Differential-

83948I-147

Data Sheet

to-LVCMOS/ LVTTL Fanout Buffer

General Description

Features

The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVT-

TL Fanout Buffer. The 83948I-147 has two selectable clock inputs.

The CLK, nCLK pair can accept most standard differential input lev-

els. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels.

The low impedance LVCMOS/LVTTL outputs are designed to drive

50 series or parallel terminated transmission lines. The effective fa-

nout can be increased from 12 to 24 by utilizing the ability of the out-

puts to drive two series terminated lines.

• Twelve LVCMOS/LVTTL outputs

• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input

• CLK/nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• LVCMOS_CLK supports the following input types:

LVCMOS, LVTTL

• Output frequency: 350MHz

The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V

core/2.5V output operating supply modes. Guaranteed output and

part-to-part skew characteristics make the 83948I-147 ideal for those

clock distribution applications demanding well defined performance

and repeatability.

• Additive phase jitter, RMS: 0.14ps (typical)

• Output skew: 100ps (maximum), 3.3V 5%

• Part-to-part skew: 1ns (maximum), 3.3V 5%

• Operating supply modes:

• Core/Output

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Block Diagram

Pin Assignment

CLK_EN

32 31 30 29 28 27 26 25

CLK_SEL

GND

LVCMOS_CLK

CLK

nCLK

V^DDO

nCLK

CLK_SEL

CLK_EN

GND

Q10

Q11

V^DD

V^DDO

GND

10 11 12 13 14 15 16

83948I-147

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

Revision D March 30, 2016

12 3 4 5 6 7...17

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